Digital Electronics Tutorial VII : NAND and XOR implementations

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This Tutorial is VII Tutorial in the digital electronics Tutorial series and discusses the concept of NAND NAND and NOR NOR implementations. It also discusses XOR XNOR implementations and its uses in parity generation and checking.
It also introduces the concept of buffer, high impedance output.
The Tutorial discusses following topics:
Other gate types…. Why ?
NAND & NOR : Universal gates
AND-OR -> NAND-NAND | OR-AND -> NOR-NOR
Conversion between forms
Exclusive-OR and Exclusive-NOR circuits
Uses of XOR / XNOR
XOR Implementations
XOR-XNOR identities
Odd and Even functions
Parity generators and checkers
Buffer
High Impedance Output
3 state buffer
Wired Output : resolving output value


Type: ppt

Discussion
Presentation Transcript Presentation Transcript

Autosketch Drawing : Digital Electronics Presentation on Lecture 8 : NAND and XOR Implementations Presented By : Parag Parandkar Assistant Professor, ECE Email: parag.vlsi@gmail.com, Contact: +919826139931 1

Equation : Acknowledgement The presenter would like to thank and acknowledge for the adoption of slides from Electrical and Computer engineering , university of Massachusetts Amherst. The presenter would also like to thank and acknowledge for the adoption of slides from Logic and Computer Design fundamentals 4 th Edition by Charles Kime and Thomas for 2008 Pearson Education limited. The copyrights belongs to the original author. The presentation is being used for educational and non commercial purpose.

Digital Electronics : Contents Other gate types…. Why ? NAND & NOR : Universal gates AND-OR -> NAND-NAND | OR-AND -> NOR-NOR Conversion between forms Exclusive-OR and Exclusive-NOR circuits Uses of XOR / XNOR XOR Implementations XOR-XNOR identities Odd and Even functions Parity generators and checkers Buffer High Impedance Output 3 state buffer Wired Output : resolving output value

Acknowledgement : Other Gate Types Why? Low cost implementation Useful in implementing Boolean functions Convenient conceptual representation Gate classifications Primitive gate - a gate that can be described using a single primitive operation type (AND or OR ) plus optional inversion(s). Complex gate - a gate that requires more than one primitive operation type for its description Primitive gates will be covered first

Contents : NAND Gate The basic NAND gate has the following symbol and truth table: AND-Invert (NAND) Symbol: NAND represents NOT AND. The small “bubble” circle represents the invert function The NAND gate is implemented efficiently in CMOS technology in terms of chip area and speed X Y X · Y X Y NAND 0 0 1 1 0 1 0 1 1 1 1 0

Other Gate Types : NAND Gate: Invert-OR Symbol Applying DeMorgan's Law: Invert-OR = NAND This NAND symbol is called Invert-OR Since inputs are inverted and then ORed together AND-Invert & Invert-OR both represent NAND gate Having both makes visualization of circuit function easier Unlike AND, the NAND operation is NOT associative (X NAND Y) NAND Z ≠ X NAND (Y NAND Z) X Y X + Y = X · Y = NAND

NAND Gate : NAND gates can implement any Boolean function NAND gates can be used as inverters, or to implement AND / OR operations A NAND gate with one input is an inverter AND is equivalent to NAND with inverted output OR is equivalent to NAND with inverted inputs The NAND Gate is Universal X Y X · Y X · Y X Y X · Y ≡ X · Y= X+Y X Y X + Y ≡ X Y X Y

NAND Gate: Invert-OR Symbol : NOR Gate The basic NOR gate has the following symbol and truth table: OR-Invert (NOR) Symbol: NOR represents NOT OR. The small “bubble” circle represents the invert function. The NOR gate is also implemented efficiently in CMOS technology in terms of chip area and speed X Y X + Y X Y NOR 0 0 1 1 0 1 0 1 1 0 0 0

The NAND Gate is Universal : NOR Gate: Invert-AND Symbol The Invert-AND symbol is also used for NOR This NOR symbol is called Invert-AND, since inputs are inverted and then ANDed together OR-Invert & Invert-AND both represent NOR gate Having both makes visualization of circuit function easier Unlike OR, the NOR operation is NOT associative (X NOR Y) NOR Z ≠ X NOR (Y NOR Z) X Y X · Y = X + Y = NOR

NOR Gate : The NOR Gate is also Universal NOR gates can implement any Boolean function NOR gates can be used as inverters, or to implement AND / OR operations A NOR gate with one input is an inverter OR is equivalent to NOR with inverted output AND is equivalent to NOR with inverted inputs X Y X + Y X + Y X Y X + Y ≡ X Y X Y X + Y= X · Y X Y X · Y ≡

NOR Gate: Invert-AND Symbol : NAND-NAND & NOR-NOR Networks DeMorgan’s Law: (a + b)’ = a’ b’ (a b)’ = a’ + b’ a + b = (a’ b’)’ (a b) = (a’ + b’)’ push bubbles or introduce in pairs or remove pairs.

The NOR Gate is also Universal : NAND-NAND Networks Mapping from AND/OR to NAND/NAND

NAND-NAND & NOR-NOR Networks : Implementations of Two-level Logic Sum-of-products AND gates to form product terms ( minterms ) OR gate to form sum Product-of-sums OR gates to form sum terms ( maxterms ) AND gates to form product

NAND-NAND Networks : Two-level Logic using NAND Gates Replace minterm AND gates with NAND gates Place compensating inversion at inputs of OR gate

Implementations of Two-level Logic : Two-level Logic using NAND Gates (cont’d) OR gate with inverted inputs is a NAND gate de Morgan's: A' + B' = (A • B)' Two-level NAND-NAND network Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed

Two-level Logic using NAND Gates : Conversion Between Forms Convert from networks of ANDs and ORs to networks of NANDs and NORs Introduce appropriate inversions ("bubbles") Each introduced "bubble" must be matched by a corresponding "bubble" Conservation of inversions Do not alter logic function Example: AND/OR to NAND/NAND A B C D Z A B C D Z NAND NAND NAND

Two-level Logic using NAND Gates (cont’d) : Z = [ (A • B)' • (C • D)' ]' = [ (A' + B') • (C' + D') ]' = [ (A' + B')' + (C' + D')' ] = (A • B) + (C • D) ü Conversion Between Forms (cont’d) Example: verify equivalence of two forms A B C D Z A B C D Z NAND NAND NAND

Conversion Between Forms : Conversion to NAND Gates Start with SOP (Sum of Products) circle 1s in K-maps Find network of OR and AND gates

Conversion Between Forms (cont’d) : A B C D E F G X Multi-level Logic x = A D F + A E F + B D F + B E F + C D F + C E F + G Reduced sum-of-products form – already simplified 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!) 25 wires (19 literals plus 6 internal wires) x = (A + B + C) (D + E) F + G Factored form – not written as two-level S-o-P 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate 10 wires (7 literals plus 3 internal wires)

Conversion to NAND Gates : Level 1 Level 2 Level 3 Level 4 original AND-OR network A C D B B C’ F introduction and conservation of bubbles A C D B B C’ F redrawn in terms of conventional NAND gates A C D B’ B C’ F Conversion of Multi-level Logic to NAND Gates F = A (B + C D) + B C'

Multi-level Logic : A X B C D F (a) Original circuit A X B C D F (b) Add double bubbles at inputs D’ A X’ B C F (c) Distribute bubbles some mismatches D’ A X B C F X’ (d) Insert inverters to fix mismatches Conversion Between Forms Example

Conversion of Multi-level Logic to NAND Gates : Exclusive-OR and Exclusive-NOR Circuits Exclusive-OR (XOR) produces a HIGH output whenever the two inputs are at opposite levels.

Conversion Between Forms : Exclusive-NOR (XNOR) : Exclusive-NOR (XNOR) produces a HIGH output whenever the two inputs are at the same level. Exclusive-NOR Circuits

Exclusive-OR and Exclusive-NOR Circuits : XNOR gate may be used to simplify circuit implementation. Exclusive-NOR Circuits

Exclusive-NOR Circuits : XOR Function XOR function can also be implemented with AND/OR gates (also NANDs). Exclusive OR Implementations

Exclusive-NOR Circuits : XOR Function Even function – even number of inputs are 1. Odd function – odd number of inputs are 1. Map of 3-variable Exclusive-OR function

XOR Function : Uses for XOR / XNOR SOP Expressions for XOR/XNOR: The XOR function is: The eXclusive NOR (XNOR) function, know also as equivalence is: Uses for the XOR and XNORs gate include: Adders/ subtractors /multipliers Counters/ incrementers / decrementers Parity generators/checkers Strictly speaking, XOR and XNOR gates do no exist for more that two inputs. Instead, they are replaced by odd and even functions. Y X Y X Y X + = Å Y X Y X Y X + = Å

XOR Function : XOR Implementations X Y X Y X Y X Y SOP implementation for XOR: X  Y = X Y + X Y NAND only implementation for XOR:

Uses for XOR / XNOR : Additional Gates and Circuits – 29 XOR / XNOR Identities XOR and XNOR are associative operations = X 0 X Å = X 1 X Å 1 X X = Å 0 X X = Å X Y Y X Å = Å ) = X  Y  Z Z Y ( X Z ) Y X ( Å Å = Å Å Y = X  Y X Y X Å = Å ) = X  Y  Z Z Y ( X Z ) Y X ( Å Å = Å Å

XOR Implementations : Odd Function The XOR function can be extended to 3 or more variables For 3 or more variables, XOR is called an odd function The function is 1 if the total number of 1’s in the inputs is odd 1 1 1 1 YZ X 00 01 11 10 0 1 1 1 1 1 YZ WX 00 01 11 10 00 01 1 1 1 1 11 10 X  Y  Z W  X  Y  Z + + + = Å Å Z Y X Z Y X Z Y X Z Y X Z Y X

XOR / XNOR Identities : Odd and Even Functions The 1s of an odd function correspond to inputs with an odd number of 1s The complement of an odd function is called an even function The 1s of an even function correspond to inputs with an even number of 1s Implementation of odd and even functions use trees made up of 2-input XOR or XNOR gates

Odd Function : Odd/Even Function Implementation Design a 3-input odd function with 2-input XOR: 3-input odd function: F = (X  Y)  Z Design a 4-input even function with 2-input XOR and XNOR gates: 4-input even function: F = (W  X)  (Y  Z) X Y Z F W X Y F Z

Odd and Even Functions : Parity Generators and Checkers A parity bit added to n -bit code produces ( n +1)-bit code with an odd (or even) count of 1s Odd Parity bit: count of 1s in ( n +1)-bit code is odd So use an even function to generate the odd parity bit Even Parity bit: count of 1s in ( n +1)-bit code is even So use an odd function to generate the even parity bit To check for odd parity Use an even function to check the ( n +1)-bit code To check for even parity Use an odd function to check the ( n +1)-bit code

Odd/Even Function Implementation : Parity Generator & Checkers Design an even parity generator and checker for 3-bit codes Solution: Use 3-bit odd function to generate even parity bit Use 4-bit odd function to check for errors in even parity codes Operation: (X,Y,Z) = (0,0,1) gives (X,Y,Z,P) = (0,0,1,1) and E = 0 If Y changes from 0 to 1 between generator and checker, then E = 1 indicates an error X Y Z P X Y Z E P Sender Receiver n -bit code Parity Generator ( n +1)-bit code Parity Checker Error

Parity Generators and Checkers : XOR gates used to implement the parity generator and the parity checker for an even-parity system. Parity Generation and Checking

Parity Generator & Checkers : Buffer A buffer is a gate with the function F = X In terms of Boolean function, a buffer is the same as a connection! So why use it? A buffer is used to amplify an input signal Permits more gates to be attached to output Also, increases the speed of circuit operation X F X F 0 1 0 1

Parity Generation and Checking : Hi-Impedance Output Logic gates introduced thus far … Have 1 and 0 output values Cannot have their outputs connected together Three-state logic adds a third logic value: Hi-Impedance output: Hi-Z What is Hi-Impedance output? The output appears to be disconnected from the input Behaves as an open circuit between gate input & output Hi-Z state makes a gate output behave differently: Three output values: 1, 0, and Hi-Z Hi-impedance gates can connect their outputs together

Buffer : The 3-State Buffer IN = data input EN = Enable control input OUT = data output If EN = 0 then OUT = HI-Z Regardless of the value on IN Output disconnected from input If EN = 1, then OUT =IN Output follows the input value Variations: EN can be inverted OUT can be inverted By addition of bubbles to signals IN EN OUT EN IN OUT 0 X Hi-Z 1 0 0 1 1 1 Symbol Truth Table

Hi-Impedance Output : Wired Output: Resolving Output Value The output of 3-state buffers can be wired together At most one 3-state buffer can be enabled. Resolved output is equal to the output of the enabled 3-state buffer If multiple 3-state buffers are enabled at the same time then conflicting outputs will burn the circuit Resolution Table O0 O1 O2 OUT 0 or 1 Hi-Z Hi-Z O0 Hi-Z 0 or 1 Hi-Z O1 Hi-Z Hi-Z 0 or 1 O2 Hi-Z Hi-Z Hi-Z Hi-Z 0 or 1 0 or 1 0 or 1 Burn IN0 EN0 OUT IN1 EN1 IN2 EN2 O0 O1 O2

The 3-State Buffer : Terms of Use All (or portions) of this material © 2008 by Pearson Education, Inc. Permission is given to incorporate this material or adaptations thereof into classroom presentations and handouts to instructors in courses adopting the latest edition of Logic and Computer Design Fundamentals as the course textbook. These materials or adaptations thereof are not to be sold or otherwise offered for consideration. This Terms of Use slide or page is to be included within the original materials or any adaptations thereof.

Parag Parandkar
Assistant Professor in Electronics
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