Teaches following Subjects/Exams
Electrical and Computer Engineering (Bachelor of Science: Electrical Engineering)
Language of Instruction:
Electronics, Networks, Digital Communication, Signal processing, Programming C, Embedded Systems, AVR ARM 8051, Enggineering Maths, FPGA's, Matlab.
University of Leicester, Leicestershire, United Kingdom
Jan 2010 - Jul 2012
Microprocessor Design and Assembly programming, Programming Reliable Embedded Systems, Using FPGA's Embedded Systems, Condition monitoring and Control.
Teaching Undergraduate and Master's studens. These courses are extensively Lab based, i designed and evaluated the course and class work.
NWFP University of Engineering and technology, Pakistan
Mar 2002 - Dec 2006
Computer Networks, Advanced Digital Design, Electronics, Signal processing, Microcontroller programming
Taught at Undergraduate Level
Senior Systems Engineer
TTE Systems Ltd, United Kingdom
Apr 2010 - Jul 2012
I am currently working as a Senior Systems Engineer with TTE systems limited, working on the Soft-core integration of an indigenous Time Triggered Processor and Field Bus protocols for Embedded system design.
University of Leicester, United Kingdom
Jan 2007 - Apr 2011
P.hD in Embedded Systems with emphasis on Real-time communication protocols.
M.Sc Computer Engineering
University of Engineering and Technology Taxxila, Pakistan
Jan 2002 - Feb 2004
Specialized in Computer Networks and Digital Communications
B. Electrical Engineering
University of Engineering and Technology Peshawar, Pakistan
Mar 1996 - Dec 2000
Specialized in Communications and Microprocessor Design
Professional Exams & Certifications
Year Of Passing:
Have done routing and switching track
Year Of Passing:
Publications and Research
Timely recovery from task failures in non-preemptive, deadline-driven schedulers
M.Short and Imran Sheikh
Published at IEEE ICESS 2010 conference, Bradford, UK.
This paper presents a simple Overrun Detection and Recovery Mechanism (ODRM) that may help to alleviate single tasking issues in npEDF, by detecting task failures in such a fashion that subsequent task deadlines are not missed in a `domino-style' manner.