EECE144 Logic Design Fundamentals
1. Course Title: Logic Design Fundamentals
2. Course ID: EECE144
3. Course Units: 4(2-2-1-8)
Lecture: 30 hours
Lab: 6 x 2 hours
4. Replacement/Equivalent Courses: -
5. Expected Participants: Third-year students in Undergraduate Advanced Programs.
6. Requisites
Prerequisites: - EECE 315, EECE 316
Requisites: -
Corequisites: -
7. Objectives and Expected Outcomes
Course Objectives:
teach number systems and Boolean Algebra; be proficient in the use of theorems and laws to manipulate Boolean expressions
demonstrate the use of logic gates, truth tables, and combinational circuit
teach students to design, simplify, and build combinational circuits
show students how to implement circuits using MSI components
explain the use of sequential logic, flip-flops, registers, counters, and state sequence generators
show how to implement digital systems design with programmable logic devices
demonstrate the use of software tools to simulate digital circuits and systems
Course Outcomes:
Students shall be able to:
apply principles of Boolean algebra to minimize logic functions
minimize Boolean functions using Karnaugh maps
Students shall be able to design, simulate, analyze, and test:
combinational circuits using Boolean algebra and K-map to simplify and optimize circuit design
a multiplexer, demultiplexer, decoder, and encoder using logic gates
a flip-flop using either NAND or NOR gates
a parallel input/parallel output, parallel input/serial output, serial input/parallel output, serial input/ serial output register using logic gates
a 4-bit synchronous binary counter using D, J-K, and T flip-flops
a state machine generating arbitrary sequence using flip-flops and logic gates
a divide-by-10 frequency counter using J-K flip-flops
8. Description
Definition and properties of switching algebra. Minimization of algebraic function. Use of Karnaugh maps for simplification. Design of combinational logic networks. Design of sequential logic devices including flip-flops, registers, and counters. Analysis and applications of digital devices. Analysis and design of synchronous and asynchronous sequential state machines, state table derivation and reduction. Use of such CAD tools for schematic capture and logic device simulations.
9. Student Duties
Class attendance: ≥ 80%
Homework: Assignments given during lectures, due at the start of class on the assigned due
date.
Lab work: Group assignments, done in teams of three. Each member will act as team leader,
on a rotating basis. A typed, clearly written lab report is required for each lab assignment per
team. The lab report should include the following sections:
Cover page
Table of contents
Objectives
Procedure
Observations
Analysis
Conclusion
References (if any)
Appendix (if any).
The front page shall be signed by each of the team members to indicate their approval. Lab
reports are due the week following the completion of the lab experiments. Late work will not be
accepted.
Exams: There will be two exams, a midterm and a final. Both will be based on material from
lectures and the course text.
10. Assessment
Homework 20%
Lab work: 20%
Midterm 30%
Final Exam (multichoice and writing): 30%
11. Course Materials
Textbook: Introduction to Logic Design, 2nd Edition, Alan B. Marcovitz, McGraw-Hill, 2005
Lecture Notes: Handout of Lectures
Lab Manual: Catalog Manual of IC used for Lab work.
12. Course Topics
LOGIC DESIGN FUNDAMENTALS
1 Introduction
1.1. A Brief Review of Number Systems
1.1.1 Decimal and Binary
1.1.2 Octal and Hexadecimal
1.1.3 Binary Addition
1.1.4 Signed Numbers
1.1.5 Binary Subtraction
1.1.6 Binary Coded Decimal (BCD)
1.1.7 Other Codes
1.2 Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra
1.2.2 Basic Properties of Switching Algebra
1.2.3 Manipulation of Algebraic Functions
1.2.3 Representations of Algebraic Functions
a. Truth Tables
b. Karnaugh Map
c. Temporal Diagram
1.2.4 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates
2. Function Minimization Methods
2.1 Algebraic Method
2.2 The Karnaugh Map
2.2.1 Minimum Sum of Product Expressions Using the Karnaugh Map
2.2.2 Don’t Cares
2.2.3 Product of Sums
2.2.4 Minimum Cost Gate Implementation
2.2.5 Five- and Six-Variable Maps
2.2.6 Multiple Output Problems
2.3 Quine-McCluskey Method
2.3.1 Quine-McCluskey Method for One Output
2.3.2 Iterated Consensus for One Output
2.3.3 Prime Implicant Tables for One Output
2.3.4 Quine-McCluskey for Multiple Output Problems
2.3.5 Iterated Consensus for Multiple Output Problems
2.3.6 Prime Implicant Tables for Multiple Output Problems
3. Larger Combinational Systems
3.1 Delay in Combinational Logic Circuits
3.2 Adders and Other Arithmetic Circuits
3.2.1 Adders
3.2.2 Subtractors and Adder Subtractors
3.2.3 Comparators
3.3 Decoders
3.4 Encoders and Priority Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.7 Three-State Gates
3.8 Gate Arrays-ROMs, PLAs and PALs
3.8.1 Designing with Read-Only Memories
3.8.2 Designing with Programmable Logic Arrays
3.8.3 Designing with Programmable Array Logic
3.9 Larger Examples
3.9.1 Seven-Segment Displays
3.9.2 An Error Coding System
Sequential Systems
Definitions
State Tables and Diagrams
Latches and Flip Flops
Analysis of Sequential Systems
Design of Sequential Systems
4.5.1 Flip Flop Design Techniques
4.5.2 The Design of Synchronous Counters
4.5.3 Design of Asynchronous Counters
4.5.4 Derivation of State Tables and State Diagrams
Solving Larger Sequential Problems
4.6.1 Shift Registers
4.6.2 Counters
4.6.3 Programmable Logic Devices (PLDs)
4.6.4 Design Using ASM Diagrams
4.6.5 On-Short Encoding
Hardware Design Languages
Verilog
VHDL
13. Lab works
Breadboard Simulator (BB): Using WINBREADBOARD for building combinational circuits such as: MUX 2-1, DEMUX 1-2
Hardware Logic Lab (HW): Design two asynchronous counters with base 16, 10 and a base 8 synchronous counter using JK Flip Flops.
Hardware Logic Lab (HW): Design a serial adder to add two 4-bit numbers. Each number is stored in a shift register using D Flip Flops.
14. References
Introduction to Logic Design, 2nd Edition, Alan B. Marcovitz, McGraw-Hill, 2005
Complete Digital Design A Comprehensive Guide to Digital Electronics and Computer System Architecture, Mark Balch, McGraw-Hill, 2003
Electronic - Digital Design Fundamentals, 2nd Edition, Kenneth J. Breeding, Prentice Hall, 1992
Fundamentals of Digital Logic with VHDL, Stephen Brown, Zvonko Vranesic, McGraw-Hill, 2005
Verilog HDL - A Guide to Digital Design and Synthesis. 2nd Edition, Samir Palnitkar, Prentice Hall, 2007
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