6.004-14, Non-pipelined Beta implementation

MIT OpenCourseWarehttp://ocw.mit.edu For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. 6.004 Computation Structures Spring 2009 L14 – Building a Beta 1 6.004 – Spring 20093/31/09Building the Beta Lab #5 due Thursday L14 – Building a Beta 2 6.004 – Spring 20093/31/09CPU Design TradeoffsMinimum Cost : measured by the size of the circuit. Best Performance/Price:measured by the ratio of MIPS to size. In power-sensitive applications MIPS/Watt is important too. Maximum Performance:measured by the numbers of instructions executed per second L14 – Building a Beta 3 6.004 – Spring 20093/31/09Performance Measure MIPS =Clock Frequency (MHz) C.P.I. Millions of Instructions per Second Clocks per instruction PUSHING PERFORMANCE ... TODAY: 1 cycle/inst. LATER: more MHz via pipelining L14 – Building a Beta 4 6.004 – Spring 20093/31/09The Beta ISA Instruction classes distinguished by OPCODE: OP OPC MEM Transfer of Control OpCode 6Operate class: Reg[Rc] Reg[Ra] op Reg[Rb] 655511Ra Rc Rb(UNUSED)01XXXXOperate class: Reg[Rc] Reg[Ra] op SXT(C) 16Ra Rc Literal C (signed) 11XXXXOpcodes, both formats: ADDSUBMUL*DIV**optionalCMPEQ CMPLECMPLT ANDORXORSHLSHRSRALD: Reg[Rc] Mem[Reg[Ra]+SXT(C)] ST: Mem[Reg[Ra]+SXT(C)] Reg[Rc] JMP: Reg[Rc] PC+4; PC Reg[Ra] BEQ: Reg[Rc] PC+4; if Reg[Ra]=0 then PC PC+4+4*SXT(C) BNE: LDR: Reg[Rc] Mem[PC + 4 + 4*SXT(C)] Reg[Rc] PC+4; if Reg[Ra]0 then PC PC+4+4*SXT(C) Ra Rc Literal C (signed) 10XXXXAdjust stick figure appearance.Figure by MIT OpenCourseWare.L14 – Building a Beta 5 6.004 – Spring 20093/31/09Approach: Incremental Featurism Each instruction class can be implemented using a simple component repertoire. We’ll try implementing data paths for each class individually, and merge them (using MUXes, etc). Steps: 1. Operate instructions 2. Load & Store Instructions 3. Jump & Branch instructions 4. Exceptions 5. Merge data paths Our Bag of Components: Registers 01MuxesALUAB“Black box” ALU DataMemoryWDARDR/WRegisterFile(3-port)RA1RA2WAWEWDRD1RD2InstructionMemoryADMemories L14 – Building a Beta 6 6.004 – Spring 20093/31/09DQ1 0 sQDENclkMulti-Port Register Files RegisterFile(3-port)RA1RA2WAWEWDRD1RD2532CLKWrite EnableWrite AddressWrite Data(independent Read addresses)(Independent Read Data)32322 combinational READ ports*, 1 clocked WRITE port *internal logic ensures Reg[31] reads as 0 55…destaselbselENENENENclkRead Port A Read Port B Write Port L14 – Building a Beta 7 6.004 – Spring 20093/31/09Register File Timing CLKWEWAWDRARDAReg[A]Anew Reg[A]2 combinational READ ports, 1 clocked WRITE port What if (say) WA=RA1??? RD1 reads “old” value of Reg[RA1] until next clock edge! new Reg[A]tSthtPDtPDL14 – Building a Beta 8 6.004 – Spring 20093/31/09Starting point: ALU Ops Means, to BETA, Reg[R4] Reg[R2] + Reg[R3] OpCode RbRa 10(unused)0000100001000010001Rc 0000000000032-bit (4-byte) ADD instruction: First, we’ll need hardware to: • Read next 32-bit instruction • DECODE instruction: ADD, SUB, XOR, etc • READ operands (Ra, Rb) from Register File; • PERFORM indicated operation; • WRITE result back into Register File (Rc). L14 – Building a Beta 9 6.004 – Spring 20093/31/09Instruction Fetch/Decode INSTRUCTION WORD FIELDSPC+4InstructionMemoryADControl LogicCONTROL SIGNALS 00OPCODE <31:26>•use PC as memory address •add 4 to PC, load new value at end of cycle •fetch instruction from memory º use some instruction fields directly (register numbers, 16-bit constant) º use bits <31:26> to generate controls 323232•Use a counter to FETCH the next instruction: PROGRAM COUNTER (PC) L14 – Building a Beta 10 6.004 – Spring 20093/31/09ALU Op Data Path RegisterFileRA1RA2RD1RD2WAWDWERc: <25:21> PC+4InstructionMemoryADRb: <15:11>Ra: <20:16>ALUABALUFNControl LogicWERFALUFNWERF00323232WERF!Operate class: Reg[Rc] Reg[Ra] op Reg[Rb] Ra Rc Rb(UNUSED)01XXXXL14 – Building a Beta 11 6.004 – Spring 20093/31/09ALU Operations (w/constant) WARc: <25:21> PC+4InstructionMemoryADRb: <15:11>Ra: <20:16>RegisterFileRA1RA2RD1RD2ALUABWAWDWEALUFNControl LogicALUFNBSEL01C: SXT(<15:0>)BSELWERFWERF0032Operate class: Reg[Rc] Reg[Ra] op SXT(C) Ra Rc Literal C (signed) 11XXXXL14 – Building a Beta 12 6.004 – Spring 20093/31/09Load Instruction WARc: <25:21> PC+4InstructionMemoryADRb: <15:11>Ra: <20:16>RegisterFileRA1RA2RD1RD2ALUABWAWDWEALUFNControl LogicBSEL01C: SXT(<15:0>)Data MemoryRDWDR/WAdrWrWDSEL0 1 2BSELWDSELALUFNWrWERFWERF003232LD: Reg[Rc] Mem[Reg[Ra]+SXT(C)] Ra Rc Literal C (signed) 100100L14 – Building a Beta 13 6.004 – Spring 20093/31/09Store Instruction WARc: <25:21> PC+4InstructionMemoryADRa: <20:16>RegisterFileRA1RA2RD1RD2ALUABWAWDWEALUFNControl LogicBSEL01C: SXT(<15:0>)Data MemoryRDWDR/WAdrWrWDSEL0 1 2BSELWDSELALUFNWrRb: <15:11>RA2SELRc: <25:21>01RA2SELWERFWERF0032No WERF! ST: Mem[Reg[Ra]+SXT(C)] Reg[Rc] Ra Rc Literal C (signed) 100110L14 – Building a Beta 14 6.004 – Spring 20093/31/09JMP Instruction WARc: <25:21> PC+4InstructionMemoryADRa: <20:16>RegisterFileRA1RA2RD1RD2ALUABWAWDWEALUFNControl LogicBSEL01C: SXT(<15:0>)Data MemoryRDWDR/WAdrWrWDSEL0 1 2BSELWDSELALUFNWrRb: <15:11>RA2SELRc: <25:21>01RA2SELJTPCSEL01234JTPCSELWERFWERF0032PC+4JMP: Reg[Rc] PC+4; PC Reg[Ra] Ra Rc Literal C (signed) 100111L14 – Building a Beta 15 6.004 – Spring 20093/31/09BEQ/BNE Instructions Data Memory RDWDR/WAdrWrWDSEL0 1 2WAPCSEL01234JTPC+4InstructionMemoryADRb: <15:11>RA2SELRc: <25:21>01Ra: <20:16>+RegisterFileRA1RA2RD1RD2BSEL01C: SXT(<15:0>)ZALUABPC+4+4*SXT(C)WAWDWE4*SXT(<15:0>)ALUFNControl LogicZPCSELRA2SELBSELWDSELALUFNWrRc: <25:21>JTWERFWERF0032PC+4BEQ: Reg[Rc] PC+4; if Reg[Ra]=0 then PC PC+4+4*SXT(C) BNE: Reg[Rc] PC+4; if Reg[Ra]0 then PC PC+4+4*SXT(C) Ra Rc Literal C (signed) 101110Ra Rc Literal C (signed) 101101L14 – Building a Beta 16 6.004 – Spring 20093/31/09Load Relative Instruction Hey, WAIT A MINUTE.What’s Load Relative good for anyway??? I thought • Code is “PURE”, i.e. READ-ONLY; and stored in a “PROGRAM” region of memory; • Data is READ-WRITE, and stored either • On the STACK (local); or • In some GLOBAL VARIABLE region; or • In a global storage HEAP. So why an instruction designed to load data that’s “near” the instruction??? C: X = X * 123456; BETA: LD(X, r0) LDR(c1, r1) MUL(r0, r1, r0) ST(r0, X) ... c1: LONG(123456) Addresses & other large constants LDR: Reg[Rc] Mem[PC + 4 + 4*SXT(C)] Ra Rc Literal C (signed) 101111L14 – Building a Beta 17 6.004 – Spring 20093/31/09LDR Instruction Data Memory RDWDR/WAdrWrWDSEL0 1 2WAPCSEL01234JTPCIF+4InstructionMemoryADRb: <15:11>RA2SELRc: <25:21>01Ra: <20:16>+RegisterFileRA1RA2RD1RD2BSEL01C:SXT( <15:0>)ZALUABWAWDWEALUFNControl LogicZPCSELRA2SELBSELWDSELALUFNWrPC+4Rc: <25:21>PC+4+4*SXT(C)ASEL01JTASELWERFWERF00LDR: Reg[Rc] Mem[PC + 4 + 4*SXT(C)] Ra Rc Literal C (signed) 101111L14 – Building a Beta 18 6.004 – Spring 20093/31/09ExceptionsWhat if something BAD happens? •Execution of an illegal op-code •Reference to non-existent memory •Divide by zero Or, maybe, just something unanticipated… •User hits a key •A packet comes in via the network GOAL: handle all these cases (and more) in SOFTWARE:•Treat each such case as an (implicit) procedure call… •Procedure handles problem, returns to interrupted program. •TRANSPARENT to interrupted program! •Important added capability: handlers for certain errors (illegal op-codes) can extend instruction set using software (Lab 7!). L14 – Building a Beta 19 6.004 – Spring 20093/31/09Exception Processing Plan: •Interrupt running program •Invoke exception handler (like a procedure call) •Return to continue execution. We’d like RECOVERABLE INTERRUPTS for • Synchronous events, generated by CPU or system FAULTS (eg, Illegal Instruction, divide-by-0, illegal mem address) TRAPS & system calls (eg, read-a-character) • Asynchronous events, generated by I/O (eg, key struck, packet received, disk transfer complete) KEY: TRANSPARENCY to interrupted program. •Most difficult for asynchronous interrupts L14 – Building a Beta 20 6.004 – Spring 20093/31/09Implementation…How exceptions work: •Don’t execute current instruction •Instead fake a “forced” procedure call •save current PC (actually current PC + 4) •load PC with exception vector •0x4 for synch. exception, 0x8 for asynch. exceptions Question: where to save current PC + 4? •Our approach: reserve a register (R30, aka XP) •Prohibit user programs from using XP. Why? LD(R31,A,R0)LD(R31,B,R1)DIV(R0,R1,R2)ST(R2,C,R31)IllOp: PUSH(XP) Fetch inst. at Mem[Reg[XP]–4] check for DIV opcode, get reg numbers perform operation in SW, fill result reg POP(XP) JMP(XP) Forced by hardware Example: DIV unimplemented L14 – Building a Beta 21 6.004 – Spring 20093/31/09ExceptionsPC+4+4*SXT(C)ASEL01Data Memory RDWDAdrR/WWDSEL012WARc: <25:21>01XPPCJT+4InstructionMemoryADRb: <15:11>Ra: <20:16>RA2SELRc: <25:21>+RegisterFileRA1RA2RD1RD2BSEL01C: SXT(<15:0>)ZALUABJTWAWDWEALUFNControl LogicZASELBSELPCSELRA2SELWDSELALUFNWrPC+401Wr01234XAdrILLOPWASELWASELIRQWERFWERF00Other: Reg[XP] PC+4; PC “Xadr” Bad Opcode: Reg[XP] PC+4; PC “IllOp” PCSELL14 – Building a Beta 22 6.004 – Spring 20093/31/09Control Logic Implementation choices: •ROM indexed by opcode, external branch & trap logic •PLA •“random” logic (eg, standard cell gates) OPOPCLDSTJMPBEQBNELDRIllopIRQALUFNF(op)F(op)"+""+"------"A"----WERF1110111111BSEL0111------------WDSEL112--000200WR0001000000RA2SEL0----1------------PCSEL00002Z ? 1 : 0Z ? 0 : 1034ASEL0000------1----WASEL000--000011L14 – Building a Beta 23 6.004 – Spring 20093/31/09Beta: Our “Final Answer” PC+4+4*SXT(C)ASEL01Data Memory RDWDAdrR/WWDSEL012WARc: <25:21>01XPPCJT+4InstructionMemoryADRb: <15:11>Ra: <20:16>RA2SELRc: <25:21>+RegisterFileRA1RA2RD1RD2BSEL01C: SXT(<15:0>)ZALUABJTWAWDWEALUFNControl LogicZASELBSELPCSELRA2SELWDSELALUFNWrPC+401Wr01234XAdrILLOPWASELWASELIRQWERFWERF00PCSELL14 – Building a Beta 24 6.004 – Spring 20093/31/09Next Time: Tackling the Memory BottleneckIsthat all there is to building a processor??? No. You’ve gotta print up all those little “Beta Inside” stickers.