6.004-3 CMOS technology, gate design, timing

MIT OpenCourseWarehttp://ocw.mit.edu For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. 6.004 Computation Structures Spring 2009 L03 -CMOS Technology 1 6.004 – Spring 20092/10/09CMOS Technology 1. Qualitative MOSFET model 2. CMOS logic gates 3. CMOS design issues poly metal pdiffndiffmodified 2/9/09 15:07 NEXT WEEK: •TUE: no lecture •THU: Lab 1 due! •FRI: QUIZ 1!!! L03 -CMOS Technology 2 6.004 – Spring 20092/10/09Combinational Device Wish List Design our system to tolerate some amount of error Add positive noise margins VTC: gain>1 & nonlinearity Lots of gain big noise margin Cheap, small Changing voltages will require us to dissipate power, but if no voltages are changing, we’d like zero power dissipation Want to build devices with useful functionality (what sort of operations do we want to perform?)VOLVILVIHVOHVinVoutVinVoutL03 -CMOS Technology 3 6.004 – Spring 20092/10/09WLMOSFETS: Gain & non-linearity gate drain source bulkInter-layer SiO2 insulation Polysilicon wire Doped (p-type or n-type) silicon substrate Very thin (<20Å)high-quality SiO2insulating layer isolates gate from channel region. Heavily doped (n-type or p-type) diffusionsChannel region: electric field from charges on gate locally “inverts” type of substrate to create a conducting channel between source and drain. MOSFETs (metal-oxide-semiconductor field-effect transistors) are four-terminal voltage-controlled switches. Current flows between the diffusion terminals if the voltage on the gate terminal is large enough to create a conducting “channel”, otherwise the mosfet is off and the diffusion terminals are not connected. IDSW/L L03 -CMOS Technology 4 6.004 – Spring 20092/10/09FETs as switches CONDUCTION: If a channel exists, a horizontal field will cause a drift current from the drain to the source. Ehgate INVERSION:A sufficiently strong vertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain. The gate voltage when the channel first forms is called the threshold voltage --the mosfet switch goes from “off”to “on”. Evinversion happens here The four terminals of a Field Effect Transistor (gate, source, drain and bulk) connect to conductors that generate a complicated set of electric fields in the channel region which depend on the relative voltages of each terminal. pnnsource drain bulkDepletion region (no carriers) forms at PN junction. Self insulating!L03 -CMOS Technology 5 6.004 – Spring 20092/10/09FETs come in two flavors The use of both NFETs and PFETs – complimentary transistor types – is a key to CMOS (complementary MOS) logic families. ppnGDSBGSDBGSDBConnect B to GND to keep PN reverse-biased (Vp < Vn); keeps D and S insulated from B Connect B to VDD to keep PN reverse-biasednnpDSGBNFET: n-type source/drain diffusions in a p-type substrate. Positive threshold voltage; inversion forms n-type channel PFET: p-type source/drain diffusions in a n-type substrate. Negative threshold voltage; inversion forms p-type channel. L03 -CMOS Technology 6 6.004 – Spring 20092/10/09CMOS Recipe DGSSDSD““NFET Operating regions: “off”: VG < VTH,NFET “on”: VG > VTH,NFETSGDPFET Operating regions: “off”: VG > VDD + VTH,PFET “on”: VG < VDD + VTH,PFETSDSD““If we follow two rules when constructing CMOS circuits then we can model the behavior of the mosfets as simple switches: Rule #1: only use NFETs in pulldown circuits(paths from output node to GND) Rule #2: only use PFETs in pullup circuits(paths from output node to VDD)~VDD/5~ -VTH,NFETL03 -CMOS Technology 7 6.004 – Spring 20092/10/09VOLVILVIHVOHCMOS Inverter VTC VinVoutIpuIpd Steady state reached when Vout reaches value where Ipu = Ipd.When VIN is low, the nfet is off and the pfet is on, so current flows into the output node and VOUT eventually reaches VDD (= VOH) at which point no more current will flow. pfet “on” nfet “off”When VIN is high, the pfet is off and the nfet is on, so current flows out of the output node and VOUT eventually reaches GND (= VOL) at which point no more current will flow. pfet “off”nfet “on” When VIN is in the middle, both the pfet and nfet are “on” and the shape of the VTC depends on the details of the devices’ characteristics. CMOS gates have very high gain in this region (small changes in VIN produce large changes in VOUT) and the VTC is almost a step function. L03 -CMOS Technology 8 6.004 – Spring 20092/10/09Beyond Inverters: Complementary pullups and pulldowns We want complementary pullup and pulldown logic, i.e., the pulldown should be “on” when the pullup is “off” and vice versa. pulluppulldown F(A1,…,An)onoffdriven “1” offondriven “0” onondriven “X” offoffno connection Now you know what the “C” in CMOS stands for! Since there’s plenty of capacitance on the output node, when the output becomes disconnected it “remembers” its previous voltage --at least for a while. The “memory” is the load capacitor’s charge. Leakage currents will cause eventual decay of the charge (that’s why DRAMs need to be refreshed!). L03 -CMOS Technology 9 6.004 – Spring 20092/10/09CMOS complements What a nice VOH you have... Thanks. It runs in the family... conducts when VGS is high conducts when VGS is low conducts when A is high and B is high: A.BABABconducts when A is low or B is low: A+B = A.Bconducts when A is high or B is high: A+B ABABconducts when A is low and B is low: A.B = A+B L03 -CMOS Technology 10 6.004 – Spring 20092/10/09A pop quiz! ABWhat function does this gate compute? A B C 0 0 0 1 1 0 1 1 11 NAND 101682Current technology: = 45nm COST: •$3500 per 300mm wafer •300mm round wafer = (150e-3)2= .07m2•NAND gate = (82)(16)(45e-9)2=2.66e-12m2•2.6e10 NAND gates/wafer (= 100 billion FETS!) •marginal cost of NAND gate: 132n$L03 -CMOS Technology 11 6.004 – Spring 20092/10/09Here’s another… What function does this gate compute? A B C 0 0 0 1 1 0 1 1 AB10 NOR 00L03 -CMOS Technology 12 6.004 – Spring 20092/10/09General CMOS gate recipe Step 1. Figure out pulldown network that does what you want, e.g.,(What combination of inputs generates a low output) ABCStep 2. Walk the hierarchy replacing nfets with pfets, series subnets with parallel subnets, and parallel subnets with series subnets ABCSo, whats the big deal? Step 3. Combine pfet pullup network from Step 2 with nfet pulldown network from Step 1 to form fully-complementary CMOS gate. ABCABCF=A•(B+C)L03 -CMOS Technology 13 6.004 – Spring 20092/10/09A Quick Review •Acombinational device is a circuit element that has–one or more digital inputs–one or more digital outputs–afunctional specification that details the value of each output for every possible combination of valid input values –atiming specification consisting (at minimum) of an upper bound tPD on the required time for the device to compute the specified output values from an arbitrary set of stable, valid input values StaticdisciplineIf C is 1 then copy A to Y, otherwise copy B to YI will generate a valid output in no more than 2 weeks after seeing valid inputsinput Ainput Binput Coutput Y L03 -CMOS Technology 14 6.004 – Spring 20092/10/09Big Issue 1: Wires Today (i.e., 100nm): RC≈ 50ps/mm Implies > 1 ns to traverse a 20mm x 20mm chip This is a long time in a 2GHz processorVINRVoutVINCL03 -CMOS Technology 15 6.004 – Spring 20092/10/09Due to unavoidable delays… Propagation delay (tPD):An UPPER BOUND on the delay from valid inputs to valid outputs.GOAL:minimize propagation delay! ISSUE:keep Capacitances low and transistors fastVOUT < tPD< tPDVINVOLVOHVILVIHtime constant = RPD•CLtime constant= RPU•CLL03 -CMOS Technology 16 6.004 – Spring 20092/10/09Contamination Delay an optional, additional timing spec INVALID inputs take time to propagate, too... CONTAMINATION DELAY, tCDALOWER BOUND on the delay from any invalid input to an invalid outputVOUT > tCD> tCDVINVOLVOHVILVIHDo we really need tCD?Usually not… it’ll be important when we design circuits with registers (coming soon!) If tCD is not specified, safe to assume it’s 0.L03 -CMOS Technology 17 6.004 – Spring 20092/10/09The Combinational Contract ABA B 0 1 1 0 tPD propagation delay tCDcontamination delay ABMust be ___________Must be ___________Note: 1. No Promises during 2. Default (conservative) spec: tCD = 0 < tPD> tCDL03 -CMOS Technology 18 6.004 – Spring 20092/10/09Acyclic Combinational Circuits If NAND gates have a tPD = 4nS and tCD = 1nS BCAYtPD = _______ nS tCD = _______ nS 122tPD is the maximum cumulative propagation delay over all paths from inputs to outputs tCD is the minimum cumulative contamination delay over all paths from inputs to outputs L03 -CMOS Technology 19 6.004 – Spring 20092/10/09Oh yeah… one last issue Recall the rules for combinational devices:Output guaranteed to be valid when all inputs have been valid for at least tPD, and, outputs may become invalid no earlier than tCD after an input changes!ABZtPDtCDAZB001101011000ABZNOR:ABZtPDtCDMany gate implementations--e.g., CMOS— adhere to even tighter restrictions. L03 -CMOS Technology 20 6.004 – Spring 20092/10/09What happens in this case? ABZtPDtCDInput A alone is sufficient to determine the outputABZABZ0X101X100ABZ001101011000ABZNOR:Lenient NOR:LENIENT Combinational Device: Output guaranteed to be valid when any combination of inputs sufficient to determine output value has been valid for at least tPD.Tolerates transitions --and invalid levels --on irrelevant inputs! CMOS NOR: L03 -CMOS Technology 21 6.004 – Spring 20092/10/09Big Issue 2: Power Energy dissipated= C VDD2per cyclePower consumed= f n C VDD2per chip where f = frequency of charge/discharge n = number of gates /chipVINVDDCVOUT VIN moves from L to H to L VOUT moves from H to L to H C discharges and then recharges L03 -CMOS Technology 22 6.004 – Spring 20092/10/09Unfortunately… Modern chips (UltraSparc III, Power4, Itanium 2) dissipate from 80W to 150W with a Vdd ≈ 1.2V (Power supply current is ≈ 100 Amps) Hey: could we Somehow recycle the charge? Worse yet… –Little room left to reduce Vdd –nC and f continue to grow Cooling challenge is like making the filament of a 100W incandescent lamp cool to the touch! L03 -CMOS Technology 23 6.004 – Spring 20092/10/09MUST computation consume energy? (a tiny digression…) A B C 0 0 0 1 1 0 1 1 1110How energy-efficient can we make a gate? It seems that switching the input to a NAND gate will always dissipate some energy… Landauer’s Principle (1961): discarding information is what costs energy! Bennett (1973): Use reversible logic gates, not NAND, and there’s no lower bound to energy use! NAND GATE: 2 bits 1 bit (information Loss!) A B 0 0 0 1 1 0 1 1 0011P Q 0110FEYNMAN GATE: 2 bits 2 bits (information Preserving!) Bennett, Fredkin, Feynman, others: Computer systems constructed from info-preserving elements. Theory: NO lower bound on energy use! Practice: Research frontier (qubits, etc.) http://www.research.ibm.com/journal/rd/441/landauerii.pdf The fundamental physical limits of computation, Bennett & Landauer, Scientific American. Vol. 253, pp. 48-56. July 1985 http://www.research.ibm.com/journal/rd/176/ibmrd1706G.pdf L03 -CMOS Technology 24 6.004 – Spring 20092/10/09Summary •CMOS•Only use NFETs in pulldowns, PFETs in pullups mosfets behave as voltage-controlled switches •Series/parallel Pullup and pulldown switch circuits are complementary •CMOS gates are naturally inverting (rising input transition can only cause falling output transition, and vice versa). •“Perfect” VTC (high gain, VOH = VDD, VOL = GND) means large noise margins and no static power dissipation.•Timing specs •tPD: upper bound on time from valid inputs to valid outputs •tCD: lower bound on time from invalid inputs to invalid outputs •If not specified, assume tCD = 0 •Lenient gates: output unaffected by some input transitions•Next time: logic simplification, other canonical forms