CMOS VLSI Design Tutorial 1

CMOS VLSI DESIGN LECTURE -1 Presented By : Parag Parandkar Assistant Professor, ECE Department , Chameli Devi School of Engineering, Khandwa road, Indore, M.P. , India Contact: parag.vlsi@gmail.com +919826139931(M)ACKNOWLEDGEMENT The Presenter would like to thank and acknowledge the authors Weste, Harris of International (3rd)edition of the book CMOS VLSI Design. The figures used in this presentation are copyright @2005 by Pearson Education, Inc. and are taken from e-book version of the book opened in WindjView software. The presenter would also like to acknowledge slides from Digital Integrated Circuits from Rabaey and from CMOS VLSI Design 4th Edition by Weste & Harris.COURSE GOALS  Learn to design and analyze state-of-the-art digital VLSI chips using CMOS technology  Employ hierarchical design methods  Understand design issues at the layout, transistor, logic and register-transfer levels Use integrated circuit cells as building blocks   Use commercial design software in the lab  Understand the complete design flow Book: Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, AW, 3rd editionCONTENTS  Types of IC Designs  MOS Technology Trends  Challenges in Digital Design  Why Scaling  Design Abstraction Levels  Transistor Types Moore’s Lay   Feature Size  Silicon Lattice  MOS Transistors  NMOS and PMOS Transistors  Power Supply Voltage  Transistor as Switches  Application of CMOS as Inverter, Nand gate and Nor gateTYPES OF IC DESIGNS  IC Designs can be Analog or Digital  Digital designs can be one of three groups  Full Custom  Every transistor designed and laid out by hand  ASIC (Application-Specific Integrated Circuits)  Designs synthesized automatically from a high-highleeve language description  Semi-Custom  Mixture of custom and synthesized modules Moore’s Law: In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 monthsMOS TECHNOLOGY TRENDSSYSTEM ON A CHIP Source: ARMSILICON LATTICE Si Si Si Si Si Si Si Si Si  Transistors are built on a silicon substrate  Silicon is a Group IV material  Forms crystal lattice with bonds to four neighbors DOPANTS  Silicon is a semiconductor  Pure silicon has no free carriers and conducts poorly  Adding dopants increases the conductivity  Group V: extra electron (n-type)  Group III: missing electron, called hole (p-type) A s S i S i S i S i S i S i S i S i B S i S i S i S i S i S i S i S i -+ +-P-N JUNCTIONS  A junction between p-type and n-type semiconductor forms a diode.  Current flows only in one direction p -type n-type a node cathodeTRANSISTOR TYPES  Bipolar transistors – npn or pnp silicon structure  – Small current into very thin base layer controls large currents between emitter and collector – Base currents limit integration density   Metal Oxide Semiconductor Field Effect Transistors – nMOS and pMOS MOSFETS  – Voltage applied to insulated gate controls current between source and drain  – Low power allows very high integrationMOS TRANSISTOR  Digital Applications: Used as Ideal Switch  The MOS transistor is a majority-carrier device in which the current in a conducting channel between the source and drain is controlled by a voltage applied to the gate.  In an nMOS transistor, the majority carriers are electrons; in a pMOS transistor, the majority carriers are holes.  Two Types: NMOS (n-channel MOS) and PMOS (p-channel MOS)NMOS TRANSISTOR Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor  Gate and body are conductors  SiO2 (oxide) is a very good insulator Called metal – oxide – semiconductor (MOS)  capacitor  Even though gate is no longer made of metal n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ BodyNMOS OPERATION Body is usually tied to ground (0 V) When the gate is at a low voltage:  P-type body is at low voltage  Source-body and drain-body diodes are OFF  No current flows, transistor is OFF n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ D 0 SNMOS OPERATION CONT. When the gate is at a high voltage:  Positive charge on gate of MOS capacitor  Negative charge attracted to body  Inverts a channel under gate to n-type  Now current can flow through n-type silicon from source through channel to drain, transistor is ON n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ D 1 SPMOS TRANSISTOR Similar, but doping and voltages reversed  Body tied to high voltage (VDD)  Gate low: transistor ON  Gate high: transistor OFF  Bubble indicates inverted behavior SiO2 n Gate Source Drain bulk Si Polysilicon p+ p+POWER SUPPLY VOLTAGE GND = 0 V In 1980’s, VDD = 5V VDD has decreased in modern processes  High VDD would damage modern tiny transistors  Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …TRANSISTORS AS SWITCHES We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g = 0 g = 1 g sd sd sd g sd sd sd nMOS pMOS OFF ON ON OFFCMOS INVERTER A Y 0 1 VDD A Y 1 0 A Y GNDCMOS NAND GATE A B Y 0 0 1 0 1 1 1 0 1 A Y 1 1 0 BCMOS NOR GATE A B Y 0 0 1 0 1 0 1 0 0 AB 1 1 0 Y3-INPUT NAND GATE Y is pulled low if ALL inputs are 1 Y is pulled high if ANY input is 0 Y AB C