Very High Speed Integrated Circuit Hardware Description Language Lecture - VI : Very High Speed Integrated Circuit Hardware Description Language Lecture - VI Presented By : Parag Parandkar
Assistant Professor,
Chameli Devi School of Engg., Khandwa Road, Indore (M.P.), India – 452020
Email: parag.vlsi@gmail.com, parag.parandkar@cdgi.edu.in
Contact: +919826139931
Acknowledgement : Acknowledgement The Presenter would like to thank and acknowledge the power point presentation slides of VHDL – A Comprehensive tutorial by anonymous.
Iterative Control : Iterative Control In this control the execution iterates over the statements until some condition is met
VHDL provides iterative control inform three kinds of loop statements
Simple loop
for loop
while loop
Simple Loop : Simple Loop Simple loop encloses a set of statements in a structure which is set to loop forever
General Form is
loop_label : loop
statements
end loop loop_label;
Example : Example P1 : process
variable A : Integer :=0;
variable B : Integer;
begin
Loop1 :loop
A := A + 1;
B := 20;
Loop2 :loop
B := B - A;
end loop Loop2;
end loop Loop1;
wait;
end process;
For Loop, While Loop : For Loop, While Loop General Form of for loop:
loop_label:
for loop_variable in range loop
statements
end loop loop_label;
General Form of while loop:
loop_label:
while condition loop
statements
end loop loop_label;
Example : Example P1 : process
variable B : Integer := 1;
begin
Loop1:
for A in 1 to 10 loop
B := 20;
Loop2:
while B >= (A * A) loop
B := B - A;
end loop Loop2;
end loop Loop1;
wait;
end process;
Exit Statement : Exit Statement Exit statement is a sequential statement closely associated with loops and causes the loop to be exited
Exit statement has two general forms :
exit loop_label;
exit loop_label when condition;
P1 : process
variable A, B : Integer :=0;
begin
Loop1 :loop
A := A + 1;
B := 20;
exit Loop1 when A = 20;
end loop Loop1;
end process;
Next Statement : Next Statement Next statement is used to advance control to the next iteration of the loop
General Form is : next loop_label when condition;
Example :
for j in 1 to 10 loop
if var1 = var2 then
next;
elsif var1 < var2
var1 := var1 + 1;
else
null;
end if;
k := k + 1;
end loop; When next statement is executed,
execution jumps to the end of the loop,
i.e last statement k := k + 1, is not
executed. Loop identifier j increments
and then loop execution resumes with
new value of j.
Assertion Statement : Assertion Statement The assertion statement has the syntax
assert condition report message severity level;
When the condition is FALSE the message is sent to system output with an indication of the severity of the message
The severity levels are Note, Warning, Error and Failure
If no message is given the default message is “Assertion Violation”. The default level is Error
Example
assert (A = B)
report “A is not equal to B”
severity Error;
Concurrent Signal Assignment : Concurrent Signal Assignment A concurrent signal assignment statement represents an equivalent process that assigns values to signals
Simple example of concurrent signal assignment is target_sig <= source_sig after delay_period;
It is one of the primary mechanisms for modeling the data-flow behavior of an entity
There are two forms of concurrent signal assignment :
1) conditional signal assignment
2) selected signal assignment
Example : Example architecture arch_sub of sub is
begin
process (in1, in2)
begin
Out1 <= In1 - In2 after Delay;
end process;
end arch_sub;
Conditional Signal Assignment : Conditional Signal Assignment This is a special form of concurrent signal assignment. Signal Assignment is done when condition is true.
General Form is:
target <= options
waveform1 when condition1 else
.
.
waveformN-1 when conditionN-1 else
waveformN;
The behavior is similar to that of an if statement in a process statement
Example : Example architecture Conditional of AND_gate is
begin
Y <= transport
‘1’ after Delay when A=‘1’ and B=‘1’ else
‘0’ after Delay;
end Conditional; architecture ConditionalEq of
AND_gate is
begin
process(A,B)
begin
if A=‘1’ and B=‘1’ then
Y <= transport ‘1’ after Delay;
else
Y <= transport ‘0’ after Delay;
end process;
end ConditionalEq;
Selected Signal Assignment : Selected Signal Assignment Selected Signal Assignment behaves very much like the case statement in a process statement
General Form is:
with expression select
target <= options
waveform1 when choices1,
.
.
waveformN when choicesN;
Complete Example : Complete Example Example 1 -- A Package with a procedure modeling the functionality of an OR gate
package gate is
procedure Or_gate(signal In1, In2 : bit; signal Out1 : out bit);
end gate;
package body gate is
procedure Or_gate(signal In1, In2 : bit; signal Out1 : out bit) is
begin
Out1 <= In1 or In2;
end Or_gate;
end gate;
Half Adder : Half Adder Example 2 -- Behavioral Description of a Half Adder
entity Half_adder is
generic (
AB_to_sum : TIME := 0 ns;
AB_to_carry : TIME := 0 ns
);
port (
A : in bit;
B : in bit;
Sum : out bit;
Carry : out bit
);
end Half_adder;
Half Adder (contd.) : Half Adder (contd.) architecture Behavioral of Half_adder is
begin
process
begin
Sum <= A xor B after AB_to_sum;
Carry <= A and B after AB_to_carry;
wait on A,B;
end process;
end Behavioral;
Full Adder : Full Adder Example 2 -- Structural Description of a Full Adder that instantiates Half Adder and Uses procedure Or_gate from the package gate.
use WORK.gate.all; -- use the Package gate
entity Full_adder is
port (
A : in bit;
B : in bit;
Carry_in : in bit;
Sum : out bit;
Carry_out : out bit
);
end Full_adder;
Full Adder (contd.) : Full Adder (contd.) architecture structural of Full_adder is
component Half_adder
generic (
AB_to_sum : TIME := 0 ns;
AB_to_carry : TIME := 0 ns
);
port (
A : in bit;
B : in bit;
Sum : out bit;
Carry : out bit
);
end component;
for all : Half_adder use entity work.Half_adder(behavioral);
Full Adder (contd.) : Full Adder (contd.) signal Temp_sum : bit;
signal Temp_carry1 : bit;
signal Temp_carry2 : bit;
begin
U0 : Half_adder generic map (5 ns, 5 ns)
port map (A, B, Temp_sum, Temp_carry1);
U1 : Half_adder generic map (5 ns, 5 ns)
port map (A => Temp_sum, B => Carry_in,
Sum => Sum, Carry => Temp_carry2);
U3 : Or_gate ( Temp_carry1, Temp_carry2, Carry_out);
end structural;
Test Bench : Test Bench library STD;
use STD.standard.all;
use STD.textio.all;
library testpackage;
use testpackage.testpackage.all;
entity fa_test is -- Entity for the test bench
end fa_test;
architecture bench of fa_test is
component Full_adder -- Component declaration for Full Adder
port (
A : in bit; B : in bit; Carry_in : in bit;
Sum : out bit; Carry_out : out bit
);
end component;
for all : Half_adder use entity work.Full_adder(Structural
Test Bench (contd.) : Test Bench (contd.) signal A, B, Carry_in : bit;
signal Sum, Carry_out : bit;
signal temp : bit_vector(0 to 31);
begin
a1: Full_adder port map ( A, B, Carry_in, Sum, Carry_out);
A <= temp(31);
B <= temp(30);
Carry_in <= temp(29);
a2: process
variable sttr : line;
variable rando : integer;
file dataout : text is out "data.out";
begin
rando := 1;
Test Bench (contd.) : Test Bench (contd.) for i in 0 to 40 loop
temp <= int2vec(rando);
rando := (rando * 3)/2 +1;
wait for 1 ms;
write(sttr, string('(" A = ")); write(sttr, A);
write(sttr, string('(" B = ")); write(sttr, B);
write(sttr, string('(" Carry_in = ")); write(sttr, Carry_in);
write(sttr, string('(" Sum = ")); write(sttr, Sum);
write(sttr, string('(" Carry_out = ")); write(sttr, Carry_out);
writeline (dataout, sttr);
wait for 0 ns;
end loop;
wait;
end process;
end bench;