Very High Speed Integrated Circuit Hardware Description Language Lecture - V : Very High Speed Integrated Circuit Hardware Description Language Lecture - V Presented By : Parag Parandkar
Assistant Professor,
Chameli Devi School of Engg., Khandwa Road, Indore (M.P.), India – 452020
Email: parag.vlsi@gmail.com, parag.parandkar@cdgi.edu.in
Contact: +919826139931
Acknowledgement : Acknowledgement The Presenter would like to thank and acknowledge the power point presentation slides of VHDL – A Comprehensive tutorial by anonymous.
Behavioral Description : Behavioral Description Sequential vs Concurrent
Process Statement
Wait Statement
Behavioral Modeling - Sequential View
Signal Assignment
Delay in Signal Assignments
Variable Assignment
Sequential Statements
Conditional Control
Iterative Control
Assertion Statement
Behavioral Description (contd.) : Behavioral Description (contd.) Behavioral Modeling - Concurrent View
Concurrent Signal Assignment
Conditional Signal Assignment
Selected Signal Assignment
Resolved Signals
Sequential vs Concurrent : Sequential vs Concurrent In VHDL there are two levels at which designer must define the behavior of a discrete system; sequential and concurrent level.
The sequential level involves programming the behavior of each process that will be used in the model. Sequential statements are executed in the order in which they appear. Used for algorithmic descriptions.
A concurrent statement executes asynchronously, with no defined relative order. Concurrent statements are used for data-flow and structural descriptions
The process statement is a concurrent statement which delineates set of sequential statements. Process statements are executed concurrently but the statements inside a process statement are executed sequentially.
Process Statement : Process Statement The process statement is a concurrent statement that defines a specific behavior to be executed when the process becomes active. The behavior of the process is described with a set of sequential statements.
General Form is :
process_label:
process
declarations
begin
statements
end process;
Process Statement (Contd.) : Process Statement (Contd.) A process is either active or suspended
A process becomes active when any of the signal read by the process changes its value
All active processes are executed concurrently
A process may be suspended upon execution of a wait statement in the process. The process remains suspended until its reactivation condition is met.
Wait Statement : Wait Statement Three kind of reactivation condition can be specified in a wait statement
timeout wait for time-expression;
condition wait until condition;
signal sensitivity wait on signal-list;
Conditions can be mixed. e.g
wait on A, B until Enable = 1;
If a process is always sensitive to one set of signals, it is possible to designate sensitivity signals using a sensitivity list.
It is illegal to use wait statement in a process with a sensitivity list
Every process is executed once upon initialization
Example : Example The following process implements a simple OR gate--
--- this process is sensitive to signals In1 and In2
Or_process : process (In1, In2)
begin
Output <= In1 or In2;
end process;
--- this is equivalent to
Or_process : process
begin
Output <= In1 or In2;
wait on In1, In2;
end process;
Sequential Assignment : Sequential Assignment This assignment occurs in a process or subprogram
It is sequentially executed
There are two fundamental types of assignment
Signal Assignment
Variable assignment
Signal Assignment : Signal Assignment A signal is comprised of a current value and a projected waveform
The current value always holds the value of the signals as read by other process
The projected waveform contains scheduled values on this signal at future times;
Simplest form
signal_name <= value;
This assigns value to the current value of the signal at the beginning of the next cycle
Signal Assignment (contd.) : Signal Assignment (contd.) Delay in signal assignment
It is possible to assign values with a delay
Delay is relative to current time
If no explicit delay is specified a delta delay is assumed
General Form :
signal_value <= value after time-expression
Example : Example Consider this Example
signal A : Bit := 0;
signal B : Bit := 1;
P1 : process
begin
B <= A;
assert ( B = A) report “ B is not equal to A” severity error;
wait on B;
end process;
Will the message be printed ?
Signal Drivers : Signal Drivers A driver is a collection of value time pairs referred to as transactions
Every concurrent statement which assigns to a signal creates a driver for that signal
Only one driver is allowed for a signal unless it is a resolved signal
Initial value of the driver is taken from the default value of the declaration which is visible to the source process. If source process is in another component it is taken from the port .
Delay in Signal Assignment : Delay in Signal Assignment There are two types of delay that can be applied when assigning a time/value pair into the driver of a signal
Inertial Delay
Transport Delay
Inertial Delay : Inertial Delay Inertial delay models the delays often found in switching circuits. An input value must remain stable for a specified time (pulse rejection limit) before the value is allowed to propagate to the output.
The value appears at the output after the specified inertial-delay.
If the input is not stable for specified rejection limit (pulse rejection limit), no output change occurs.
Inertial signal assignment has the form :
signal_object <= [ [ reject pulse-rejection-limit ] inertial ]
expression after inertial-delay-value;
Example :
Z <= reject 4 ns inertial A after 10ns
Transport Delay : Transport Delay This delay models pure propagation delay; ie, any change in the input (no matter how small) is transported to the output after the specified delay time period
To use a transport delay model, the keyword transport must be used in a signal assignment statement
Ideal delay modeling can be obtained by using this delay model, where spikes would be propagated through instead of being ignored
Variable Assignment : Variable Assignment A variable is declared in a process or a subprogram
When a variable is declared with a process it retains its value throughout the simulation. i.e it is never re-initialized
Variables declared in subprograms are reinitialized whenever the subprogram is called
General Form of variable assignment is
variable_name := expression;
The variable assignment updates the value immediately after the assignment without any delay
Conditional Control : Conditional Control These sequential statements provide conditional control i.e statements are executed when a given condition is true
VHDL provides two types of conditional control statements
if then elsif
case end case
If Statement : If Statement General form is
if condition then
statement
elsif condition then
statement
else
statement
end if;
Example : Example And_process : process
begin
if In1 = ‘0’ or In2 = ‘0’ then
Out <= ‘0’ after Delay;
elsif In1 = ‘X’ or In2 = ‘X’ then
Out <= ‘X’ after Delay;
else
Out <= ‘1’ after Delay;
end if;
wait on In1, In2;
end process;
Case Statement : Case Statement General Form is
case expression is
when value =>
statements
when value | value =>
statements
when discrete_range =>
statements
when others =>
statements
end case
Example : Example Select_process : process
begin
case X is
when 1 => Out <= ‘0’;
when 2 | 3 => Out <= ‘1’;
when others =>
out <= ‘X’;
end case;
end process