Very High Speed Integrated Circuit Hardware Description Language Lecture - IV : Very High Speed Integrated Circuit Hardware Description Language Lecture - IV Presented By : Parag Parandkar
Assistant Professor,
Chameli Devi School of Engg., Khandwa Road, Indore (M.P.), India – 452020
Email: parag.vlsi@gmail.com, parag.parandkar@cdgi.edu.in
Contact: +919826139931
Acknowledgement : Acknowledgement The Presenter would like to thank and acknowledge the power point presentation slides of VHDL – A Comprehensive tutorial by anonymous.
Structural Description : Structural Description Basic Features
Component Instantiation Statement
It is concurrent statement. It can be done by -
Instantiation of a declared Component
A component is instantiated. The component needs to be bound to some actual entity(architecture) with a configuration.
Direct instantiation statement (VHDL 93 feature)
No component needs to declared. No separate binding is required. An entity(architecture) can be directly instantiated.
Block Statement
Generate Statement
Configuration Specification
Configuration Declaration
Basic Features : Basic Features Structural description of a piece of hardware is a description of what its sub-components are and how the sub-components are connected
Structural description is more concrete than behavioral description. i.e. correspondence between a given portion of description and a portion of hardware is easier to see in structural descriptions
Component Instantiation statement is basic unit of structural Description.
Component instantiation can be done by -
Instantiating a declared component and providing binding information to bind it with actual entity(architecture)
Directly instantiating an entity(architecture). No separate component declaration and binding information is needed. (: VHDL 93 feature)
Component Instantiation : Component Instantiation Component Instantiation statement specifies an instance of a component (child component) occurring inside another component (parent component)
At the point of instantiation, only the external view of the child component (the names, types and directions of ports) is visible
The statement identifies the child component and specifies the connectivity of the local signals or ports of parent component with the ports of child component
General Form of the statement
label: instantiated_unit generic map association-list
port map association-list;
instantiated_unit ::= [component] component_name
| entity entity_name [(architecture_identifier)]
| configuration configuration_name
Component Instantiation : Component Instantiation Generic/Port map associations are omitted if the corresponding component declaration lacks generics/ports
The component_name must reference a component declared by a component declaration. The component declaration need not occur in the architecture body containing the instantiation but it must be visible at the point of instantiation. (e.g through a visible package)
A port of Component Declaration is called a local
In a component instantiation statement, the port association list associates an actual with a local
The associated actual must be
an object of class signal
open
static expression if port mode is “in”
Example : Example architecture Parent_body of Parent is
component And2 -- Component Declaration
port ( I1, I2 : Bit; O1 : out Bit);
end component;
signal S1, S2, S3 : Bit;
begin
Child : And2 port map ( I1=>S1, I2=>S2, O1=>S3); -- Instance
end Parent_body;
Entity Vs Component : Entity Vs Component ENTITY
Entity is a library unit which can be compiled separately and it never occurs inside another library unit
Entity declaration declares something that really “exists” in the design library COMPONENT
Component Decl only occurs inside a library unit. It may occur inside a Package Decl or an architecture body
Component declaration merely declares a template that
does not exist in the design library
Port Association : Port Association VHDL imposes three kinds of restrictions based on type mode and resolvability, on the association of an actual with local
VHDL requires that the type of actual be the same as the type of the local
VHDL requires that if the local is readable, then the actual must also be readable, and if the local is writable, then the actual must also be writable
Association with a local of mode out or inout creates a source for the actual. It follows that an actual, which is not a resolved signal, may not be associated with more than one locals of mode out or inout
Example : Example entity Invert_8 is
port ( Inputs : in Bit_vector (1 to 8);
Outputs : out Bit_vector (1 to 8));
end Invert_8;
architecture Invert_8 of Invert_8 is
component Inverter
port ( I1 : Bit; O1 : out Bit);
end component;
begin
G: for I in 1 to 8 generate
inv : Inverter port map (Inputs(I), Outputs(I));
end generate;
end Invert_8;
Generics : Generics Generics provide a channel for static information to be communicated to a design-block from its environment.
Typical use of generics are to parameterize timing, the range of subtypes, the number of instantiated sub-components, and the size of array objects (in particular the size of ports)
Generics are declared as interface elements.
The only object type permitted is constant.
The only mode permitted is in.
Allowed inside
Entity Declarations
Component Declarations
Blocks
Example : Example entity and_gate is
generic (eg : integer);
port (eI1, eI2 : in bit_vector(1 to eg); eO : out bit_vector(1 to eg));
end;
architecture and_gate_arch of and_gate is
begin --- implementation not shown
end;
entity top is end;
architecture top of top is
signal s1, s2, s3 : bit_vector(1 to 3);
component gate
generic (cg : integer);
port (cI1, cI2 : in bit_vector(1 to cg); cO : out bit_vector(1 to cg));
end component;
for all : gate use entity work.and_gate(and_gate_arch)
generic map (eg => cg) port map (eI1 => cI1, eI2 => cI2, eO => cO);
begin
AND1 : gate generic map (cg => 3) port map (cI1 => s1, cI2 => s2, cO => s3);
end;
Block Statement : Block Statement A block statement defines an internal block representing a portion of a design. Blocks may be hierarchically nested to support design decomposition
A block may have three parts -
block header, block declarative part, block statement part
Block Header
Block header explicitly identifies certain values, signals which are to be imported from the enclosing environment into the block and associated with formal generics and ports
Block Declarative Part
Type, subtype, subprogram, constant, signal …etc can be declared in the block declarative part. These items are local to block scope.
Block Statement Part: Block statement part consists a set of concurrent statements.
Example : Example entity ent is
end;
architecture arc of ent is
signal sig_a : integer;
constant con_a : time := 1 ns;
begin
B : block
--- block header part
generic (bg : time); generic map (bg => con_a);
port (bp1 : in integer); port map (bp1 => sig_a);
--- block declarative part
signal sig_b : integer;
begin
--- block statement part
sig_b <= sig_a after bg;
end block;
end
Generate Statements : Generate Statements A generate statement provides a mechanism for iterative or conditional elaboration of a portion of description
Consists of a generation-scheme and a set of enclosed concurrent statements
Following VHDL concurrent statements may be enclosed by the generate statement
Process statement
Block Statement
Concurrent assertion statement
concurrent signal assignment
concurrent procedure call
concurrent instantiation statement
another generate statement
Generate Statements (contd.) : Generate Statements (contd.) General Form is
label-identifier : generation-scheme generate
concurrent-statements
end generate identifier;
There are two kinds of generation scheme
if-scheme
for-scheme
Example : Example entity Invert_8 is
port ( Inputs : in Bit_vector (1 to 8);
Outputs : out Bit_vector (1 to 8));
end Invert_8;
architecture Invert_8 of Invert_8 is
component Inverter
port ( I1 : Bit; O1 : out Bit);
end component;
begin
G: for I in 1 to 8 generate
inv : Inverter port map (Inputs(I), Outputs(I));
end generate;
end Invert_8;
Configuration Specification : Configuration Specification This construct allows the designer to specify the selection of entity declaration and architecture body for each component instance.
General Form is
for component_specification use binding_indication ;
component_specification
Identifies which instances are configured
Consists of an instantiation label (or a label list) followed by colon and the component name
binding_indication
Specifies mapping between the component and the entity
It may also contain a generic/port association list
Configuration Specification : Configuration Specification Example
for U1, U2 : Inverter use entity work.Inv1(Inv1_body);
for all : And_gate use entity work.And_gate1(And_gate1);
for others : Inverter use entity work.Inv2(Inv2_body);
Instantiation label allows two key words all and others
Use of all means that the configuration specification applies to all the instantiations of the given component.
Use of others means that the configuration specification applies to all the instantiations of the given component except for those instances which are already configured by the preceding configuration specifications
Configuration Declaration : Configuration Declaration Configures sub-component hierarchy.
The binding of a component instance to design entities can be performed by configuration specification which appears in the declarative part of the design-block in which the the corresponding component instance resides. Otherwise, the user can defer the binding of the component instance until later, leaving the component in the design-block unbound. Configuration declaration provides the mechanism for specifying such deferred binding.
This has following two benefits
Provides support for top-down design methodology
Allows a designer to take advantage of a library of reusable components.
Example : Example Consider the configuration declaration for an entity COMM_BOARD that fits into a full PC slot
configuration FULL_SLOT of COMM_BOARD is
for ARCH_COMM_BOARD
for CPU : PROCESSOR
use entity std_parts.SPARC(intel) generic map (Clock => 40 ns);
for intel --- component configuration for instantiations in intel
end for; --- for intel
end for; --- for PROCESSOR
… --- configuration of other different units
end for; --- for architecture ARCH_COMM_BOARD
end FULL_SLOT;