Very High Speed Integrated Circuit Hardware Description Language Lecture - II : Very High Speed Integrated Circuit Hardware Description Language Lecture - II Presented By : Parag Parandkar
Assistant Professor,
Chameli Devi School of Engg., Khandwa Road, Indore (M.P.), India – 452020
Email: parag.vlsi@gmail.com, parag.parandkar@cdgi.edu.in
Contact: +919826139931
Acknowledgement : Acknowledgement The Presenter would like to thank and acknowledge the power point presentation slides of VHDL – A Comprehensive tutorial by anonymous.
Course Coverage : Course Coverage Subprogram
Function and Procedure
Package
Package declaration and Package Body
Use Clause
Analysis Rule for Units
Objects and Data Types
Scalar Type
Literal
Subprograms : Subprograms Subprograms are of two types :
- functions and procedures
A subprogram consists of a sequence of declarations and statements which can be repeated from different locations in VHDL descriptions
subprograms can be overloaded
functions can be used for operator overloading
procedures can assign values to its parameter objects while functions can not
A subprogram can be separated into its subprogram declaration and subprogram body
Subprograms (contd.) : Subprograms (contd.) Full form of subprogram declaration is
subprogram-specification;
Two forms of subprogram - specification
procedure identifier interface_list
[pure | impure] function identifier interface_list return type_mark
Full form of subprogram body is
subprogram-specification is
declarations
begin
statements
end identifier;
Functions : Functions Intended to be used strictly for computing values and not for changing value of any objects associated with the function’s formal parameters
All parameters must be of mode in and class signal or constant or File.
If no mode is specified, the parameter is interpreted as having mode in. If no class is specified parameters are interpreted as being of class constant. Parameter of type FILE has no mode.
Examples of function declaration
Object class of parameter is implicit
function Mod_256 (X : Integer) return Byte;
Object class of parameter is explicit
function Mod_256(constant X : in Integer) return Byte;
Example : Example Function declaration
function Min (X, Y : Integer) return Integer;
-- Function Specification
function Min (X, Y : Integer) return Integer is
begin
if (X < Y) then
return X;
else
return Y;
end if;
end Min;
Procedures : Procedures Procedures are allowed to change the values of the objects associated with its formal parameters
Parameters of procedures may of mode in, out or inout
If no mode is specified the parameter is interpreted as having mode in. If no class is specified parameters of mode in are interpreted as being of class constant and parameters of mode out or inout are interpreted as being of class variable. Parameter of type FILE has no mode.
Examples of procedure declaration
Object class of parameter is implicit
procedure Mod_256 (X : inout Integer);
Object class of parameter is explicit
procedure Mod_256(variable X : inout Integer);
Example : Example Procedure declaration
--- X is of class variable
Procedure ModTwo (X : inout Integer);
-- Procedure Specification
Procedure ModTwo (X : inout Integer) is
begin
case X is
When 0 | 1 => null;
When others X := X mod 2;
end case;
end ModTwo;
Packages : Packages Allows data types, subprograms, object declarations (signal, constants, shared variables and files), component declarations etc. to be shared by multiple design units.
package identifier is
declarations
end [package] [identifier];
Example :
package logic is
type Three_level_logic is (‘0’, ‘1’, ‘z’);
function invert (Input : Three_level_logic) return
Three_level_logic;
end logic;
Package Body : Package Body Package declarations and bodies are separately described
Package declarations contain public and visible declarations
Items declared inside package body is not visible outside the package body
Package body has the same name as the corresponding package declaration
package body identifier is
declarations
end [package body] [identifier];
Package Body (contd.) : Package Body (contd.) Example of a package body for package logic
package body logic is
-- subprogram body of function invert
function invert (Input: Three_level_logic) return
Three_level_logic is
begin
case Input is
when ‘0’ => return ‘1’;
when ‘1’ => return ‘0’;
when ‘Z’ => return ‘Z’;
end invert;
end logic;
USE CLAUSE : USE CLAUSE Use clause preceding an unit makes all the elements of a package or a particular element of a package visible to the unit
An architecture body inherits the use clauses of its entity. So if those use clauses are sufficient for the descriptions inside the architecture, then no explicit use clause is necessary for the architecture
Simple examples :
Makes all items of package std_logic_1164 in library ieee visible
use ieee.std_logic_1164.all;
Makes Three_level_logic in package Logic in library work visible
use work.Logic.Three_level_logic;
Use Clause (contd.) : Use Clause (contd.) library my_lib;
use my_lib.Logic.Three_level_logic;
use my_lib.Logic.Invert;
entity Inverter is
port (X : in Three_level_logic;
Y : out Three_level_logic);
end inverter;
Analysis Rules for Units : Analysis Rules for Units Units can be separately analyzed provided following rules are obeyed
a secondary unit can be analyzed only after its primary unit is analyzed
a library unit that references another primrary unit can be analyzed only after the referred unit has been analyzed
an entity, architecture, configuration referenced in a configuration declaration must be analyzed before the configuration declaration is analyzed
A library clause makes library visible and an use clause makes the units inside the library visible to other units
library Basic_Library;
Use Basic_Library.Logic;
Use Logic.all;
Objects and Data Types : Objects and Data Types Something that can hold a value is an object (e.g signal)
In VHDL, every object has a type, the type determining the kind of value the object can hold
VHDL is strongly typed language
The type of every object and expression can be determined statically. i.e the types are determined prior to simulation.
Three basic VHDL data types are
integer types
floating point types
enumerated types
Data types can be user defined
Data Types : Data Types Data type Scalar Type Composite Type Access Type File Type Integer Float Physical Enumeration Record Array Integer and enumeration types are called discrete types Integer, Real and Physical types are called numeric types
Data Types(contd.) : Data Types(contd.) Scalar Type
Most atomic
Can be ordered along a single scale
Integer types
type Byte is range -128 to 127;
type Bit_pos is range 7 downto 0;
Floating types
type fraction_type is range 100.1 to 200.1;
Enumerated Types
consists of enumeration literal
a literal is either an identifier or a character literal
type Three_Level_Logic is (‘0’, ‘1’, ‘z’);
type Color_set is (RED, GREEN, BLUE);
Data Types : Scalar Type (contd.) : Data Types : Scalar Type (contd.) Physical Type
Values of physical type represent measurement of some physical quantity such as time, distance etc.
Any value of a physical type is an integral multiple of the primary unit of measurement for the type
Example
type Time is range -(2**31 -1) to (2**31 -1)
units
fs ; --- primary unit
ps = 1000 fs; --- secondary unit
ns = 1000 ps; --- secondary unit
end units;
Literal : Literal These are symbols whose value is immediately evident from the symbol
Six Literal Types
integer, floating, characters, strings,
bit_string and physical literal;
Examples
2 19878 16#D2# 8#720# 2#1000100
1.9 65971.3333 8#43.6#e+4 43.6E-4
“ABC()%”
B”1100” X”Ff” O”70”
15 ft 10 ohm 2.3 sec