CMOS Sequential Circuit design Lecture - 3

Introduction to CMOS Sequencial Circuit Design Lecture Series-3 : Introduction to CMOS Sequencial Circuit Design Lecture Series-3 Presented By : Parag Parandkar Assistant Professor, ECE Department , Chameli Devi School of Engineering, Khandwa road, Indore, M.P. , India Contact: parag.vlsi@gmail.com +919826139931(M)

Acknowledgement : Acknowledgement The Presenter would like to thank and acknowledge the authors Weste, Harris of International (3rd)edition of the book CMOS VLSI Design. The figures used in this presentation are copyright @ 2005 by Pearson Education, Inc. and are taken from e-book version of the book opened in WindjView software. Copyright belongs to the respective publishers. Presenter requests the book to be purchased by the learners. Without buying the requisite book you are not ideally allowed to be in the class.

Contents : Contents Acknowledgement Design of CMOS latches and flip flops Conventional CMOS latches CMOS Transparent Latches Conventional CMOS Flip Flops

Conventional CMOS Latches : Conventional CMOS Latches Conventional CMOS latches are built using pass transistors or tristate buffers to pass the data while the latch is transparent and feedback to hold the data while the latch is opaque.

Slide 5 : (a) A very simple transparent latch built from a simple nMOS transistor. It is compact and fast but has 4 limitations: i) The output does not swing from rail-to-rail, it never rises above VDD - Vt. ii) The output is also dynamic; i.e., the output floats when the latch is opaque. If it floats long enough, it can be disturbed by leakage. iii) D drives the diffusion input of a pass transistor directly, leading to potential noise issues. iv) The state node is exposed, so noise on the output can corrupt the state. (b) Uses a CMOS transmission gate in place of the single nMOS pass transistor to offer rail-to-rail output swings. It requires a complementary clock (φ)’, which can be provided as an additional input or locally generated from (φ) through an inverter. (c) adds an output inverter so that the state node X is isolated from noise on the output. Creates inverting latch.

Slide 6 : (d) behaves as an inverting latch with a buffered input but unbuffered output. Both (c) and (d) are fast dynamic latches. In modern processes, subthreshold leakage is large enough that dynamic nodes retain their values for only a short time, especially at the high temperature and voltage encountered during burn-in test. Therefore, practical latches need to be staticized, adding feedback to prevent the output from floating, as shown in (e). When the clock is '1,' the input transmission gate is ON, the feedback tristate is OFF, and the latch is transparent. When the clock is '0,' the input transmission gate turns OFF. However, the feedback tristate turns ON, holding X at the correct level. (f) adds an input inverter so the input is a transistor gate rather than unbuffered diffusion. Both (e) and (f) reintroduced output noise sensitivity. A large noise spike on the output can propagate backward through the feedback gates and corrupt the state node X.

CMOS Transparent Latches : CMOS Transparent Latches

Slide 8 : (g) is a very robust transparent latch that addresses all of the deficiencies mentioned so far. The latch is static, all nodes swing rail-to-rail, the state noise is isolated from output drives transistor gates rather than diffusion. It is recommended for all but the most performance- or area-critical designs. In semicustom datapath applications where input noise can be better controlled, the inverting latch of fig. (h) may be preferable because it is faster and more compact. (i) shows the jamb latch, a variation of (g) that reduces the clock load and saves two transistors by using a weak feedback inverter in place of the tristate. (j) shows another jamb latch commonly used in register files and Field Programmable Gate Array (FPGA) cells. Many such latches read out onto a single Dout wire and only one is enabled at any given time with its RD signal.

Slide 9 : The Itanium 2 processor uses the latch shown in Fig. (k). In the static feedback, the pulldown stack is clocked, but the pullup is a weak pMOS transistor. Therefore, the gate driving the input must be strong enough to overcome the feedback. C2MOS latch: (b) is logically equivalent but electricaly inferior because toggling D while the latch is opaque can cause charge sharing noise the output node.

Conventional CMOS Flip Flops : Conventional CMOS Flip Flops (a) shows a dynamic inverting flip-flop built from a pair of back-to-back dynamic latches. Either the first or the last inverter can be removed to reduce delay at the expense of greater noise sensitivity on the unbuffered input or output. (b) adds feedback and another inverter to produce a noninverting static flip-flop.

Slide 11 : Flip-flops usually take a single clock signal (φ) and locally generate its complement (φ)’. Recall that the flip-flop also has a potential internal race condition between the two latches. This race can be made worse by skew between the clock and its complement caused by the delay of the inverter. Transmission gates and NORA dynamic flip flops

Slide 12 : Slide 10 (a) circuit is redrawn in slide 11 (a) with a built-in clock inverter. When (φ) falls, both the clock and its complement are momentarily low as shown in Fig (b), turning on the clocked pMOS transistors in both transmission gates. If the skew (i.e., inverter delay) is too large, the data can sneak through both latches on the falling clock edge, leading to incorrect operation. (c) shows a C2MOS dynamic flip-flop built using C2MOS latches rather than inverters and transmission gates. Because each stage inverts, data passes through the nMOS stack of one latch and the pMOS of the other, so skew that turns on both clocked pMOS transistors is not a hazard. The same skew advantages apply even when an even number of inverting logic stages are placed between the latches; this technique is sometimes called NO RAce (NORA).