Introduction to CMOS Sequential Circuit Design Lecture Series-1 : Introduction to CMOS Sequential Circuit Design Lecture Series-1 Presented By :
Parag Parandkar
Assistant Professor,
ECE Department ,
Chameli Devi School of Engineering,
Khandwa road, Indore, M.P. , India
Contact: parag.vlsi@gmail.com
+919826139931(M)
Contents : Contents Acknowledgement
CMOS Sequential Circuit Design
Sequencing static Circuits
Sequencing methods
Flip flop viewed back to back latches
Timing Diagrams
Max Delay Constraints
Max-Delay flip flops, two phased latches, pulsed latches
Min delay constraints
Min-Delay flip flops, two phased latches, pulsed latches
Acknowledgement : Acknowledgement The Presenter would like to thank and acknowledge the authors Weste, Harris of International (3rd)edition of the book CMOS VLSI Design.
The figures used in this presentation are copyright @ 2005 by Pearson Education, Inc. and are taken from e-book version of the book opened in WindjView software.
CMOS Sequential Circuit Design : CMOS Sequential Circuit Design Sequential circuits : the output depends on previous as well as current inputs; said to have state.
Examples: FSM, Pipelines.
Usually designed with flip-flops or latches (memory elements), that hold data called tokens.
Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.
Inevitably adds some delay to the slow tokens.
Makes circuit slower than just the logic delay called sequencing overhead, also called as clocking overhead.
Slide 5 : Sequencing the static and dynamic circuits.
Static circuits : gates that have no clock input, examples: complementary CMOS, pseudo-nMOS, pass transistor logic.
Dynamic circuits :gates that have a clock input, e.g.
domino logic.
Sequencing elements : static or dynamic.
Static storage : Feedback to retain its output value indefinitely.
Dynamic storage: Maintains its value as charge on a capacitor that will leak away if not refreshed for a long period of time.
Sequencing Static Circuits : Sequencing Static Circuits Sequential elements: flip-flops and latches.
3 terminals incorporated by both:
data input (D), clock (elk), and data output (Q).
The latch is transparent when the clock is high and opaque when the clock is low – level sensitive.
The flip-flop: an edge-triggered device that copies D to Q on the rising edge of the clock and ignores D at all other times.
Sequencing Methods : Sequencing Methods Flip-flops
2-Phase Latches
Pulsed Latches
Flip Flop viewed as back to back latch pair : Flip Flop viewed as back to back latch pair
Timing Diagrams : Timing Diagrams Contamination and Propagation Delays
Max-Delay Constraints : Max-Delay Constraints Ideally, the entire clock cycle would be available for computations in the combinational logic.
The sequencing overhead of the latches or flip-flops cuts into this time.
If the combinational logic delay is too great, the receiving element will miss its setup time and sample the wrong value.
This is called a setup time failure or max-delay failure.
It can be solved by : redesigning the logic to be faster
or by increasing the clock period.
The computation of the actual time available for logic and the sequencing overhead of each of sequencing elements is done in next slides: flip-flops, two-phase latches, and pulsed latches.
Max-Delay: Flip-Flops : Max-Delay: Flip-Flops
Max-Delay: Flip-Flops : Max-Delay: Flip-Flops
Max Delay: 2-Phase Latches : Max Delay: 2-Phase Latches
Max Delay: 2-Phase Latches : Max Delay: 2-Phase Latches Solving for the maximum logic delay, which is the sum of the logic delays through each of the two phases.
The sequencing overhead is the two latch propagation delays.
The nonoverlap between clocks does not degrade performance in the latch-based system because data continues to propagate through the combinational
logic between latches even while both clocks are low. A flip-flop can be made from two latches whose delays determine the flop propagation delay and setup time.
Max Delay: 2-Phase Latches : Max Delay: 2-Phase Latches
Max Delay: Pulsed Latches : Max Delay: Pulsed Latches
Max Delay: Pulsed Latches : Max Delay: Pulsed Latches
Min-delay Constraints : Min-delay Constraints Ideally, sequencing elements can be placed back to back without intervening combinational logic and still function correctly.
e.g. , a pipeline can use back-to-back registers to sequence along an instruction opcode without modifying it.
However, if the hold time is large and the contamination delay is small, data can incorrectly propagate through two successive elements on one clock edge, corrupting the state of the system.
This is called a race condition, hold time failure, or min-delay failure.
It can only be fixed by : redesigning the logic,
not by slowing the clock.
Therefore, designers should be very conservative in avoiding such failures because modifying and refabricating a chip is very expensive and time-consuming.
Min-Delay: Flip-Flops : Min-Delay: Flip-Flops
Min-Delay: Flip-Flops : Min-Delay: Flip-Flops
Min-Delay: Flip-Flops : Min-Delay: Flip-Flops If the contamination delay through the flip-flop exceeds the hold time, back-to-back flip-flops can be safely used.
If not, explicitly delay must be added between the flip flops (e.g., with a buffer) or use special slow flip-flops with greater than normal contamination delay on paths that require back-to-back flops.
Scan chains are a common example of paths with back-to-back flops.
Min-Delay: 2-Phase Latches : Min-Delay: 2-Phase Latches Hold time reduced by nonoverlap
Paradox: hold applies twice each cycle, vs. only once for flops.
But a flop is made of two latches!
Min-Delay: 2-Phase Latches : Min-Delay: 2-Phase Latches Hold time reduced by nonoverlap
Paradox: hold applies twice each cycle, vs. only once for flops.
But a flop is made of two latches!
Min-Delay: Pulsed Latches : Min-Delay: Pulsed Latches Hold time increased by pulse width
Min-Delay: Pulsed Latches : Min-Delay: Pulsed Latches Hold time increased by pulse width