Verilog HDL : Verilog HDL Presented By : Parag Parandkar
Assistant Professor,
Chameli Devi School of Engg., Khandwa Road, Indore (M.P.), India – 452020
Email: , parag.vlsi@gmail.com, parag.parandkar@cdgi.edu.in
Contact: +919826139931
Slide 2 : BACKGROUND
Verilog is also an IEEE standard HDL (1364 – 1995).
It was introduced in 1985 by Gateway Design Systems as a proprietary language for their simulator verilog-XL.. Cadence acquired Verilog-XL in 1989. It was put on public domain in 1990.
Verilog is now maintained by Open Verilog inernational(OVI)
Verilog is more like C, while VHDL is more like ADA.
Verilog supports different levels of abstraction, the hardware can be described in terms of switches, gates, RTL or behavior.
Verilog is case sensitive and all reserve words is in lower
case letters.
Slide 3 : LEVELS OF ABSTRACTION In Verilog the hardware can be defined in four levels of abstraction depending on the needs of the design.
1) Behavioral or Algorithmic Level
2) Dataflow
3) Gate Level
4) Switch Level This is the lowest level of abstraction available in Verilog. Here the module is implemented in terms of switches, storage nodes and interconnections between them. Design at this level requires the knowledge of switching theory and other switch level implementation details.
Slide 4 : Building Blocks MODULE Module is the basic building block of verilog. It provides the port interfaces and the functionality of the hardware. It can be compared with VHDL entity-architecture combined. MODULE In verilog it is illegal to nest modules I.e. one module definition cannot contain another module definition within the module and endmodule statement.
Slide 5 : VHDL- VERILOG COMPARED VHDL
Entity Declaration
Architecture for the entity
Configuration Verilog
Only Module declaration.
Slide 6 : VHDL- VERILOG COMPARED Verilog
Only Module declaration.
Simpler Code
Relatively Less Features
Programming Language Interface.
Switch Level modeling possible only with verilog. VHDL
Entity Declaration
Architecture for the entity
Configuration
Behavioral level modeling good in VHDL
Many Features functions and procedures, libraries etc.
Bulky Code
Slide 7 : CHOICE OF VHDL OR VERILOG Personal preferences
EDA tool availability
Commercial, business and marketing issues.
Suitability in the level of abstraction.
Slide 8 : Scalar
Enumeration
Integer
Physical
Floating Point
Composite
Arrays
Records Only 1, 0, X, Z are defined in verilog VHDL- Verilog Compared DATA TYPES
Slide 9 : VHDL- Verilog Compared DATA TYPES VHDL
signal
time
string
integer
real
variable Verilog
wire
reg
other wire types
integer -- 32 bit
real -- 64 bit
time -- 64 bit
Slide 10 : VHDL- Verilog Operators Verilog VHDL
+ + Addition
- - Subtraction
* * Multiplication
% mod modulus
~ not unary (not)
Slide 11 : VHDL- Verilog Relational Operators Verilog VHDL
> > Greater Than
>= >= Greater than or equal
< < Less Than
<= <= Less Than or equal
== = Logical Equality
!= /= Logical Inequality
Slide 12 : Verilog Bitwise Operators ~ Negation
& AND
| OR
^ XOR
~& NAND
~| NOR
~^ XNOR
Slide 13 : Verilog Operators Miscellaneous === Case equality
!== Case inequality
{,} Concatenation
<< Left Shift
>> Right Shift
?: Conditional
Slide 14 : VERILOG Design
Slide 15 : Preliminary Verilog Codes module nandg (in1,in2,out);
input in1, in2;
output out;
assign out = ~ (in1 & in2);
endmodule
Slide 16 : assign dataflow statement In the example the continuous assign statement continuously watches for changes to variables in its RHS and whenever that happens the RHS is re-evaluated and the result is immediately propagated to the LHS.
The continuous assign statement is used to model combinational circuits where the outputs change with changes with input values.
Slide 17 : Nand Gate using assign statement & waveform
Slide 18 :
Slide 19 : Value levels in Verilog Verilog has 4 value levels 0,1,X and Z.
In addition to value levels Verilog has strengths assigned to the levels to resolve conflict between drivers of different strengths in digital circuits.
If two signals of unequal strengths drive a wire, the stronger one will prevail.
If two signal of equal strength appear on a wire then it will result in X.
Slide 20 : Nets Nets represent the interconnections between the hardware elements.
They require a driver continuously.
They are 1-bit value by default unless declared as a vector.
The default value of net is Z (except for trireg where it is X).
NET is not a keyword, but represent a class of data types as wire, and other wire data types.
Example: wire a; wire c,d = 1’b0;
Slide 21 : Registers REGISTERS represent data storage elements.
A register in verilog is a variable that can hold value till another value is placed onto them.
Unlike a net a register don't need a driver.
Declared by using the keyword reg.
Default data type is x.
Example: reg d;
Slide 22 : Vectors Both Nets and Regs can be declared as vectors
[ high # : low # ] OR
[ low # : high # ]
The leftmost number in the square bracket is always the MSB.
Example:
wire [7:0] b ----> EQ to bus ( 7 downto 0 )
Slide 23 : Parameters Constants can be defined in Verilog using the keyword parameter.
Parameter values for each module instance can be overridden at compile time ( like generics). Thus the use of parameters makes the module definition flexible.
Example: parameter N = 5;
Slide 24 : Operators Three Types:
Unary(~)
Binary (&),
Ternary ( ?:)
Unary Operator has only 1 operand
e.g.: a = ~ b ;
Binary Operator has two operands.
Ternary Operator has 3 operands
e.g.: a = b ? C : D;
Slide 25 : Number Specification ’
is written in decimal and represents the number of bits in the number.
Legal base formats are Decimal (‘d or ‘D), hexadecimal (‘h or ‘H), Octal ( ‘o or ‘O) and Binary (‘b or ‘B).
Number can be any digit from 0, 1, 2, 3, 4, 5, 6, 7, 8,9,a,b, c,d,e,f. Only a subset of these digits is
valid for a particular base format. Upper case letters are also legal.
e.g.: 4’b1111 // 4 - bit binary number 1111
16’Hffff // 16 - bit HEX number FFFF
Slide 26 : Number Specification Numbers without the base format is by default DECIMAL.
Numbers without the size specifications have default number of bits assigned to them depending on the simulator (at least 32 bits).
X or Z can be added to a binary, HEX or octal number to denote unknown or high impedance state.
If the MSB of a number is 0, x or z then the number is automatically extended to fill the MSB with 0, x or z respectively. This makes it easy to assign x or z to whole vectors.
“?” can be used in context of numbers as an alternative to z.
“_” Underscore can be used at any place in numbers except the first character to improve readability.
Slide 27 : System tasks Verilog language provides has inbuilt routines to do certain tasks like displaying data, monitoring signals, starting and stopping simulations etc., these are called System Tasks
SYNTAX:
$
Some commonly used system tasks are listed in the following slides
Slide 28 : Commonly used System Tasks $display (p1, p2, p3, …. , pn);
This is the main system task for displaying values of variables, strings, expressions etc.
It is like the printf command in C.
It inserts a newline at the end of a string by default.
$display( “ Hello World”);
$display($time); // prints current simulation time
$display( “Result is %b”, sum);
Slide 29 : Strings can be formatted as in C using the following String Format Specifications Strings %d or %D Display variable in decimal
%b or %D Display variable in binary
%s or %S Display String
%h or %H Display variable in Hex
%c or %C Display ASCII Character
%v or %V Display strength
%o or %O Display variable in Octal
%e or %E Display Real Number (Sci. Format)
%f or %F Display Real Number (decimal Format)
%g or %G Display Real Number (Sci. or Dec. whichever is shortest)
Slide 30 : MONITORING INFORMATION $monitor ( p1,p2,p3 … pn) It has a format similar to $display.
This system task continuously monitors the values of variables or signals mentioned in the parameter list and displays all the parameters in the list whenever the value of any one of the variable or signal changes.
$monitor needs to be invoked only once.
Only one monitor list can be active at a time. If there are more than one monitor statements in the module then the last one is the active statement.
$monitoron and $monitoroff can be used to control the monitoring during simulation.
Slide 31 : Syntax:
1) $monitor (p1, p2, p3, ……….. Pn);
2) $monitoron;
3) $monitoroff; EXAMPLE:
$monitor ($time, “CLOCK = %b Reset = %b D = %b “, clk, rst, D)
Slide 32 : STOPPING AND FINISHING SIMULATION $stop can be used to stop during simulation.
This helps to make the simulation more interactive and helps in debugging.
$finish terminates the simulation. EXAMPLES:
initial
Begin
#100 $stop // suspend simulation at time 100
#900 $finish // terminate simulation at time 1000
end
Slide 33 : COMPILER DIRECTIVES USAGE: ‘ ‘define is similar to the #define in C.
Example:
‘define S $stop; // alias for $stop can be used by putting ‘S ‘include is similar to #include in C. This is commonly used to include header files that contain commonly used definitions.
Example:
‘include header.v; // include a file header.v for compilation.
Slide 34 : INITIAL STATEMENT Verilog is concurrent programming language . To incorporate sequential structured operations INITIAL and ALWAYS statement constructs are used. The INITIAL statement will be explained first. SYNTAX
initial
begin
…………..
……………
end
Slide 35 : INITIAL block starts at simulation time 0 and executes exactly once during a simulation and then does not execute again.
There can be multiple INITIAL blocks in a module and all execute concurrently at time 0.
Each INITIAL block will finish its execution independent of the other blocks.
To specify delay the format is :
# =
The initial blocks are typically used for initialization, monitoring, making waveforms and other process that must be executed only once during the entire simulation run.
Slide 36 : ALWAYS STATEMENT always
………………. The always statement starts at simulation time 0 and continuously executes the statements inside the block in a looping fashion.
This is used to model clocks or other digital elements whose activity is repeated continuously .
The ALWAYS block can be seen as an infinite loop and the only way to stop it is by the $finish or $stop system tasks.
Slide 37 : WRITING TEST BENCHES: Structural Mapping of components:
module XOR(in1,in2,out);
input in1, in2;
output out;
…………….
……………………
XOR u1 (.in1(a),.in2(b),.out(c));
Slide 38 : module xor_tst;
reg a,b;
wire c;
XOR u1 (.in1(a),.in2(b),.out(c));
initial
begin
b = 1'b0;
end
initial
begin
a = 1'b0;
end always
#10 b = ~b;
always
#5 a = ~a;
endmodule TEST BENCH FOR XOR GATE
Slide 39 : PORTS AND PORT CONNECTION RULES Ports provide interface for the module to communicate with its environment.
The internals of the module is not visible to the environment, this helps the designer to change the internal without effecting the environment as long as the interface in left untouched.
Ports are also referred to as terminals.
Ports can be of type: Input, Output or Bi-directional and the verilog keywords for declaring them are: input, output, inout.
Slide 40 : Input Output Inout If a port is intended to be a wire, then it is sufficient to declare it as input, output or inout.
If a port has to hold its value then it must be again declared as reg.
Ports of type input or inout cannot be declared as reg because reg variables store values and input port should not store value, but simply reflect the changes in the external signals they connect.
Slide 41 : PORT CONNECTION RULES These are rules governing port connections when modules are instantiated within other modules. net net Inout Input Output net Reg or net Reg or net net Ports can be visualized as consisting of two units one internal to the module and the other external to the module.
Slide 42 : RULES: Inputs : Internally input ports must always be of type net. Externally, inputs can be connected to a reg or a net.
Outputs: Internally they can be of type reg or net. Externally they must be connected to a net only, they cannot be connected to a reg.
Inouts: Internally and Externally they are always connected to type net only.
Slide 43 : RULES: Unconnected Ports: Verilog allows ports to remain unconnected .
e.g. : Fulladd fa1 ( sum , ,a, b, cin); Unconnected Port Width Matching: It is legal to connect Internal and External items of different sizes with making inter-module port connections. A warning will be issued by the simulator when widths don’t match. Positional Association
Slide 44 : GATE PRIMITIVES In verilog some basic Logic gates are predefined and they are known as primitives.
These primitives can be instantiated like other modules.
There are two classes basic gate primitives in verilog. And / or Buf / not AND / OR
and nand
or nor
xor xnor BUF / NOT
buf not
And other buf and not primitives GATE LEVEL MODELLING
Slide 45 : AND / OR They have one scalar output and multiple scalar inputs.
The first terminal of the gate is an output and the other terminals are inputs.
The output terminal is denoted by out.
The input terminals is denoted by i1 and i2.
The output of the gate is evaluated as soon as one of the input changes.
More than 2 inputs can be specified in a gate instantiation. Verilog will automatically instantiates the appropriate gate. Outputs for the gates with more than 2 inputs are calculated by applying the corresponding truth table iteratively.