Introduction to CMOS Sequencial Circuit Design Lecture Series-2 : Introduction to CMOS Sequencial Circuit Design Lecture Series-2 Presented By :
Parag Parandkar
Assistant Professor,
ECE Department ,
Chameli Devi School of Engineering,
Khandwa road, Indore, M.P. , India
Contact: parag.vlsi@gmail.com
+919826139931(M)
Contents : Contents Acknowledgement
Time borrowing
Maximum amount of time borrowing
Time borrowing for pulsed latches
Pros of time borrowing
Clock skew
Clock slew max delay in flip flop
Clock slew min delay in flip flop
Latch based systems are skew tolerant
Clock skew for pulsed latches
Clock skew sum up
Acknowledgement : Acknowledgement The Presenter would like to thank and acknowledge the authors Weste, Harris of International (3rd)edition of the book CMOS VLSI Design.
The figures used in this presentation are copyright @ 2005 by Pearson Education, Inc. and are taken from e-book version of the book opened in WindjView software.
Time borrowing : Time borrowing Flip-flops : data departs the first flop on the rising edge of the clock and must set up at the second flop before the next rising edge of the clock.
If the data arrives late, the circuit produces the wrong result.
If the data arrives early, it is blocked until the
clock edge, and the remaining time goes unused.
Flip flop clock induces hard edge.
In transparent latches, data can depart the first latch on rising edge of clock but does not have to set up until the falling edge of the clock on the receiving latch.
If one half-cycle or stage of a pipeline has too much logic, it can borrow time into the next half-cycle or stage.
Slide 5 :
Slide 6 : In Fig. (b) shows a single-cycle self- bypass loop in which time borrowing occurs across half-cycles, but the entire path must fit in one cycle.
Self-bypass loop example: execution stage of a pipelined processor; an ALU must complete an operation and bypass the result back for use
in the ALU on a dependent instruction.
Most critical paths in digital systems occur in
self-bypass loops.
Maximum amount of time borrowing : Maximum amount of time borrowing
Maximum amount of time borrowing : Maximum amount of time borrowing Because data does not have to set up until the falling edge of the receiving latch's clock, one phase can borrow up to half a cycle of time from the next (less setup time and non- overlap):
Time borrowing for pulsed latches : Time borrowing for pulsed latches Pulsed latches can be viewed as transparent latches with a narrow pulse.
If the pulse is wider than the setup time, pulsed latches are also capable of a small amount of time
borrowing from one cycle to the next.
Pros of Time Borrowing : Pros of Time Borrowing i) Intentional time borrowing: the designer can more easily balance logic between half-cycles and pipeline stages. This leads to potentially shorter design time because the balancing can take place during circuit design rather than requiring changes to the microarchitecture to explicitly move functions from one stage to another.
ii) Opportunistic time borrowing: Even if the designer carefully equalizes the delay in each stage at design time, the delays will differ from one stage to another in the fabricated chip because of process and environmental variations and inaccuracies in the timing model used
by the CAD system. In a system with hard edges, the longest cycle sets the minimum clock period.
Slide 11 : In a system capable of time borrowing, the slow cycles can opportunistically borrow time from faster ones and average out some of the variation.
Some experienced designers avoid intentional time borrowing until chip reaches its tapeout, otherwise designers are overly prone to assuming that their pipeline stage can borrow.
When many designers make this same assumption, all of the paths become excessively long.
The problem may be hidden until full chip timing analysis begins, at which time it is too late to redesign so many paths.
Another solution is to do full-chip timing analysis starting early in the design process.
Clock Skew : Clock Skew Generally clocks are assumed to be ideal having zero skew.In reality clocks have some uncertainty in their arrival times that can cut into the time available for full computation.
Clock skew for max delay in FF : Clock skew for max delay in FF The worst scenario for max delay in a flip-flop-based system is that the launching flop receives its clock late and the receiving flop receives its clock early.
In this case, the clock skew is subtracted from the time available for useful computation and appears as sequencing overhead.
This is illustrated in Fig. (a) of previous page.
Clock skew for min delay in FF : Clock skew for min delay in FF
Clock skew for min delay in FF : Clock skew for min delay in FF The worst scenario for min delay is that the launching flop receives its clock early and the receiving clock receives its clock late, as shown in Fig. (b) in the previous slide.
The clock skew effectively increases the hold time of the system, in this case.
Latch based systems are skew tolerant : Latch based systems are skew tolerant In the system using transparent latches, clock skew does not degrade performance.
Reason:
The full cycle (less two latch delays) is available for computation even when the clocks are skewed because the data can still arrive at the latches while they are transparent.
However, skew still effectively increases the hold time in each half-cycle.
It also cuts into the window available for time borrowing.
Latch based systems are skew tolerant : Latch based systems are skew tolerant
Clock Skew for pulsed latches : Clock Skew for pulsed latches Pulsed latches can tolerate an amount of skew proportional to the pulse width.
If the pulse is wide enough, the skew will not increase the sequencing overhead because the data
can arrive while the latch is transparent.
If the pulse is narrow, skew can degrade performance.
Just like in case of two phase latches, for pulsed latches too, skew effectively increases the hold time and reduces the amount of time available for borrowing .
Clock Skew Sump up : Clock Skew Sump up Systems with hard edges (e.g., flip-flops) subtract clock skew from the £ne available for useful computation.
Systems with softer edges (e.g., latches) take advantage of the window of transparency to tolerate some clock skew without increasing the sequencing overhead.
Nearby sequential elements are likely to see less skew than elements on opposite corners of the chip.
Current automated place & route tools put lot of effort to model clock delays and insert buffer elements to minimize clock skew, but skew is a growing problem for systems with aggressive cycle times.