Sujith R Asst. Professor, Dept. of ECE, KRGCEWContents Contents • Combinational Circuits • Sequential Circuits • Logic families – Multivibrator using gates • Finite state machines • Combinational Circuits • Sequential Circuits • Logic families – Multivibrator using gates • Finite state machines © Dept. of ECE,KRGCEW – Hazards • Introduction to VHDL • Applications of basic digital modules – Hazards • Introduction to VHDL • Applications of basic digital modulesq Objective § At the end of this session , we will be able to design the basic digital modules. Similar modules are discussed in context -Application of Basic Digital Modules © Dept. of ECE,KRGCEWCombinational Circuits Combinational CircuitsIntroduction © Dept. of ECE,KRGCEW © Dept. of ECE,KRGCEWDecoder © Dept. of ECE,KRGCEW3 to 8 line Decoder A2 A1 A0 X0 X1 X2 X3 X4 X5 X6 X7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 © Dept. of ECE,KRGCEW 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 Follow conventional notations. Letter S for select S0,s1,s2 etc, (LSB to MSB)…., D for Data input, Y for Output, Decoder operation© Dept. of ECE,KRGCEWAssignments • BCD to Decimal Decoder(4-10 line decoder) • 4 to 16 line decoder • Active Low and Active High Decoder Ics • IC 74138,IC7442 • Design 4-16 line decoder by using 3-8 line decoder (74138) • Implement the following expressions using a single Decoder © Dept. of ECE,KRGCEW F1=Σm(2,3,9,11) F2=Σm(10,12,13,14) (Hint : Page No302 , digital fundamentals, A.Anandkumar) Encoder (8-3 Line) DATA A2 A1 A0 D0 0 0 0 D1 0 0 1 D2 0 1 0 © Dept. of ECE,KRGCEW D3 0 1 1 D4 1 0 0 D5 1 0 1 D6 1 1 0 D7 1 1 1 Decimal to BCD Encoder © Dept. of ECE,KRGCEW Priority Encoders If more than one inputs are applied simultaneously, o/p will be corresponding to higher order i/p © Dept. of ECE,KRGCEW When D2=1 & D1=1 output Y0=1,Y1=1 Corresponding to D3 When D2=1 & D1=1 output Y0=0,Y1=1 Corresponding to D2 Q. Ckt Of Octal to Binary Priority Encoder ? Decimal to BCD Priority Encoder • Let the outputs are A0 A1 A2 A3(LSB to MSB) • A0 is high if, D1 is High and D2,D4,D6,D8 are Low D3 is High and D4,D6,D8 are Low D5 is High and D6,D7 are Low © Dept. of ECE,KRGCEW D7 is High and D8 is Low D9 is High A0= D1 D2’D4’D6’D8’+D3 D4’D6’D8’+D5 D6’D8’+D7 D8’+D9 A1=? A2=? A3=? Assignments • key board encoders • Priority encoder • IC 74147 • Difference b/w Active Low & Active High © Dept. of ECE,KRGCEW Encoders Multiplexer Sel A B out 0 0 0 0 0 0 1 0 0 1 0 1 Sel Out 0 A Ξ © Dept. of ECE,KRGCEW 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 1 B 4:1 MUXA B OUT 0 0 C0 0 1 C1 © Dept. of ECE,KRGCEW 1 0 C2 1 1 C3 When A=0 ,B=0 àC0 is selected Ie, out is 1 if C0=1 or Out is 0 If C0=0. No other input affects the output8 to 1 Mux (Using NAND) © Dept. of ECE,KRGCEW ? Contd.. © Dept. of ECE,KRGCEW ENABLEAssignments • Mux IC 74151, 74150 • Realization of 16 input Mux from Two 8 input Mux’s • Draw the circuit of 4:1 Mux with an active low Enable line, active low Data input , active low select lines & © Dept. of ECE,KRGCEW Active low output. • Implement the following Boolean expression using i) 16:1Mux ii) 8:1 Mux f(A,B,C,D)=Σm(10,12,13,14) • Applications of Mux De-MuxSel Q0 Q1 0 In 0 © Dept. of ECE,KRGCEW 1 0 In When Sel = 0, Q0=1 if in=1 and Q0=0 if in = 0. Q1 will not be affected Q.Draw Ckt. Diagram ? 1 to 8 De-mux A2 A1 A0 X0 X1 X2 X3 X4 X5 X6 X7 0 0 0 D 0 0 0 0 0 0 0 0 0 1 0 D 0 0 0 0 0 0 0 1 0 0 0 D 0 0 0 0 0 0 1 1 0 0 0 D 0 0 0 0 © Dept. of ECE,KRGCEW 1 0 0 0 0 0 0 D 0 0 0 1 0 1 0 0 0 0 0 D 0 0 1 1 0 0 0 0 0 0 0 D 0 1 1 1 0 0 0 0 0 0 0 DMUX & De-MUX Application Mod 3 counter Mod 3 counter Q0 Q1 S0 S1 Q0 Q1 S0 S1 Clock Clock User 1 © Dept. of ECE,KRGCEW Synchronization is required to eliminate mismatch in transmitter & receiver called Time division multiplexing MUX DE-MUX User 2 User 3Demux using Decoder © Dept. of ECE,KRGCEW Assignments • IC 74138 • Uses of De-Mux • Active Low & Active High Mux &De-Mux • What is meant by ENABLE signal of an IC? © Dept. of ECE,KRGCEW • Decoder, Encoder, Mux, DeMux Circuits With ENABLE Signals. Half Adder A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 © Dept. of ECE,KRGCEW 1 1 0 1 Ckt With 2 inputs & 2 Outputs SUM= AB’+A’B = A X-OR B Carry= ABFull Adder © Dept. of ECE,KRGCEW Expressions Simplification SUM = A’B’C+A’BC’+AB’C’+ABC = A’(B’C+BC’)+A(B’C’+BC) = A’ (B X-OR C)+A (B X-OR C)’ = A B C © Dept. of ECE,KRGCEW X-OR X-OR CARRY = A’BC+AB’C+ABC’+ABC = C ( A X-OR B)+AB(C+C’) = C ( A X-OR B)+AB Assignments • Implement Full Adder Using Half Adders • Realize Full & Half adder Using only NAND gates • Realize Full & Half adder Using only NOR gates (Hint: Page 238. Digital Funtamentals, A.Anandkumar) © Dept. of ECE,KRGCEW Half & Full Subtractor A B Bin D B 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 A B D B 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 © Dept. of ECE,KRGCEW 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 Difference D = A X-OR B Borrow B = A’B Difference D = A X-OR B X-OR Bin Borrow B = A’B+(A X-OR B)’ Bin Q. Draw Ckt. Diagrams? Parallel Adder or Ripple carry Adder(4 Bit) =GND © Dept. of ECE,KRGCEW Disadvantage : C3 will be generated only after the propagation delay of three full adders Q. What is propagation Delay??? Q. What is Serial Adder??? Look Ahead Carry Adder (To overcome the propagation delay) © Dept. of ECE,KRGCEW Full Adder that Produces CG &CP Functions © Dept. of ECE,KRGCEW CP (Carry Propagated) à when any of the i/p is 1 CG (Carry Generated) à When both of the i/ps are 1Look Ahead carry Adder © Dept. of ECE,KRGCEW Expressions © Dept. of ECE,KRGCEW Full-adder FA3 ???© Dept. of ECE,KRGCEW BCD Adder S4 S3 S2 S1 S0 Decimal 0 1 0 1 0 10 0 1 0 1 1 11 0 1 1 0 0 12 0 1 1 0 1 13 0 1 1 1 0 14 0 1 1 1 1 15 1 0 0 0 0 16 1 0 0 0 1 17 1 0 0 1 0 18 Invalid Outputs © Dept. of ECE,KRGCEWAssignments • 8 bit parallel adder • Serial adder • IC 7483 © Dept. of ECE,KRGCEW See Also, • 1’s complement and 2’s complement representations • 1’s complement and 2’s complement Arithmetic Comparator(1 bit) © Dept. of ECE,KRGCEW Comparator (2 Bit) © Dept. of ECE,KRGCEW Algorithm • Start Checking from MSB • If MSB of A =1& B=0 àA>B (ie AB’=1) • If MSB of A & B are EQUAL (either 0 or 1), Check the next LSB Bit. And so on….. For Eg: Two Four bit Numbers 1100,1110Assignments • 4 Bit Comparator • Applications of comparator © Dept. of ECE,KRGCEW Home Assignments ΘImplement the following Boolean expression f(A,B,C)=Σm(3,4,5) using i)8:1Mux ii) 4:1 Mux iii)3:8 Decoder ΘDraw the Circuit of 3:8 Decoder with active low output and with active low enable signal. © Dept. of ECE,KRGCEW ΘDraw the circuit of full subtractor using NAND gates. ΘPerform Addition of the following decimal numbers by using BCD Addition. 1399+3282=? Θ Represent an AND gate in canonical forms. Θ Realize XOR gate using 2:1 MuxSequential Circuits Sequential CircuitsSequential Circuits © Dept. of ECE,KRGCEWBasic SR Latch © Dept. of ECE,KRGCEW _S _RQN+1 Comment 0 0 invalid 0 1 0 Set 1 0 1 Reset 1 1 QN No change S R QN+1 Comment 0 0 QN No change 0 1 0 Reset 1 0 1 Set 1 1 ? InvalidBasic SR Latch working S R QN QN+1 Comment 0 0 0 0 No change 0 0 1 1 0 1 0 0 Reset 0 1 1 0 © Dept. of ECE,KRGCEW 1 0 0 1 Set 1 0 1 1 1 1 0 ? Invalid 1 1 1 ? QN+1 à Present state QN à Previous stateCharacteristic Equation of SR Latch S R QN QN+1 Comment 0 0 0 0 No change 0 0 1 1 00 01 11 10 QN+1 © Dept. of ECE,KRGCEW 0 1 0 0 Reset 0 1 1 0 1 0 0 1 Set 1 0 1 1 1 1 0 ? Invalid 1 1 1 ? 01 0 1 0 0 1 1 x x _ QN+1= R QN + SGated SR Latch © Dept. of ECE,KRGCEW S R EN QN+1 0 0 HIGH QN 0 1 HIGH 0 1 0 HIGH 1 1 1 HIGH ?JK Flip flop © Dept. of ECE,KRGCEWCharacteristic Equation of JK Flipflop J K QN QN+1 Comment 0 0 0 0 No change 0 0 1 1 00 01 11 10 QN+1 KQN J © Dept. of ECE,KRGCEW 0 1 0 0 Reset 0 1 1 0 1 0 0 1 Set 1 0 1 1 1 1 0 1 Toggle 1 1 1 0 01 0 1 0 0 1 1 0 1 _ _ QN+1= K QN + J QN D Flip-Flop PRE CLK D Q 0 0 1 1 © Dept. of ECE,KRGCEW CLR Characteristic equation QN+1= DT Flip-Flop © Dept. of ECE,KRGCEW CLK T Q 0 QN 1 _ QN _ _ QN+1= T QN + T QN Characteristic equationDifferent Types of Triggering © Dept. of ECE,KRGCEW +ve Edge Triggered F/F -ve Edge Triggered F/F Level Triggered F/F+ve going Edge detecting Circuit © Dept. of ECE,KRGCEWWaveforms of Edge triggered JK F/F © Dept. of ECE,KRGCEWWaveforms of Different Triggering CLK D input © Dept. of ECE,KRGCEW +ve Level Triggered F/F +ve edge Triggered F/F -ve Edge Triggered F/F Q output Q output Q outputMaster Slave Flip-flops • To avoid race around condition • If j=1 & k=1 , and clk remains high for a long duration, then output keeps on changing and is known as race around condition. • Master slave flip-flop is also called pulse © Dept. of ECE,KRGCEW triggered flip-flopMaster Slave D Flip-flop © Dept. of ECE,KRGCEWContd.. © Dept. of ECE,KRGCEWWaveform © Dept. of ECE,KRGCEWExcitation Table © Dept. of ECE,KRGCEWConversion of Flip-flops © Dept. of ECE,KRGCEW Q _QConversion of Flip-flops © Dept. of ECE,KRGCEWAssignments • Conversion of – D to JK – D to T – JK to D © Dept. of ECE,KRGCEW – SR to JK – T to D – SR to DShift Registers • Serial In Serial Out Shift Register • Serial In Parallel Out Shift Register • Parallel In Parallel Out Shift Register • Bi-Directional Shift Register © Dept. of ECE,KRGCEW • Universal Shift RegisterSerial in Parallel /Serial out Shift register © Dept. of ECE,KRGCEWBi-directional Shift register © Dept. of ECE,KRGCEWCounters • Synchronous Counters (CLK common) • Asynchronous Counters © Dept. of ECE,KRGCEWAsynchronous Counters (Ripple Counters) © Dept. of ECE,KRGCEWContd… © Dept. of ECE,KRGCEWDecade(Mod-10) Asynchronous Counter © Dept. of ECE,KRGCEWPropagation delay Problem in ripple counter 0 1 2 3 4 5 6 7 8 9 © Dept. of ECE,KRGCEWSynchronous Counters Mod-6 Synchronous Counter © Dept. of ECE,KRGCEWContd… © Dept. of ECE,KRGCEWMod-6 synchronous Counter (Contd..) © Dept. of ECE,KRGCEWSynchronous Up/Down Counter © Dept. of ECE,KRGCEWContd.. © Dept. of ECE,KRGCEW àJ2, K2,J1,K1 ???? àLogic Realization ??Home Assignments • BCD synchronous Counter • Count the sequence 0,4,1,5,2,6,3,7,0,4,1… using D, T flip-Flops © Dept. of ECE,KRGCEW Ring Counter ___ PRE © Dept. of ECE,KRGCEWJohnson Counter © Dept. of ECE,KRGCEWLogic Families Logic FamiliesLogic Families – TTL • Classic 74-series • High power consumption • Low noise margin – CMOS © Dept. of ECE,KRGCEW • Low power consumption • High noise margin – ECL • Extremely fast • High power consumption • Small voltage swingVoltage Parameters – VIH(min): high-level input voltage, the minimum voltage level required for a logic 1 at an input. – V (max): low-level input voltage, The maximum © Dept. of ECE,KRGCEW VIL(voltage level that can be treated as logic 0 at input – VOH(min): high-level output voltage – VOL(max): low-level output voltageCurrent Parameters – IIH(min): high-level input current, the current that flows into an input when a specified high-level voltage is applied to that input. – IIL(max): low-level input current © Dept. of ECE,KRGCEW – IOH(min): high-level output current – IOL(max): low-level output currentPropagation Delays – tpLH: delay time in going from logical 0 to logical 1 state (LOW to HIGH) – tpHL: delay time in going from logical 1 to logical 0 state (HIGH to LOW) © Dept. of ECE,KRGCEW – Measured at 50% points.Power Requirements – Every IC needs a certain amount of electrical power to operate. – Vcc (TTL) – VDD(MOS) © Dept. of ECE,KRGCEW – Power dissipation determined by Icc and Vcc. – Average Icc(avg)= (ICCH + ICCL)/2 – PD(avg) = Icc(avg) x Vcc• Noise Immunity • What happens if noise causes the input voltage to drop below VIH(min) or rise above VIL(max)? • The noise immunity of a logic circuit refers to the circuit’s ability to tolerate noise without causing spurious changes in the output voltage © Dept. of ECE,KRGCEW • Fan-Out • The maximum number of standard logic inputs that an output can drive reliably.Characteristics IDEAL 0-5V OUTPUT © Dept. of ECE,KRGCEW PRACTICALTTL NAND GATE © Dept. of ECE,KRGCEWTTL NAND gate with output low © Dept. of ECE,KRGCEWTTL NAND gate with output high © Dept. of ECE,KRGCEWTTL NOT GATE © Dept. of ECE,KRGCEWTTL NOR gate circuit © Dept. of ECE,KRGCEW • Output is high only when A and B are low. • In this case both Q1 and Q2 are on, Q3 and Q4 are off, and Q6 if off. • Otherwise, if A or B is high, Q6 is on and output is low. Q2 and Q4 added to TTL inverterTTL NOR gate circuit © Dept. of ECE,KRGCEW •When A is high, Q3 and Q6 is on, and output is low •When B is high, Q4 and Q6 is on, and output is low TTL NOR gate circuit © Dept. of ECE,KRGCEW •Output is high only when A and B are low. • In this case both Q1 and Q2 are on, Q3 and Q4 are off, and Q6 is off.TTL NOR /OR GATE © Dept. of ECE,KRGCEW4-INPUT ECL OR /NOR GATE M1 M2 M3 M4 N K © Dept. of ECE,KRGCEW If ANY or ALL input(s) is/are HIGH , Transistor(s) M corresponding to HIGH input(s), is/are ON and N is OFF à NOR output is LOW Transistors K1 is ON à OR output is HIGHCMOS NOT Gate +++ ---© Dept. of ECE,KRGCEW + -When Gate is +ve P-channel MOSFET is OFF N-channel MOSFET is ONCMOS NOR GATE © Dept. of ECE,KRGCEWTRI-STATE GATE © Dept. of ECE,KRGCEW Q. Draw Circuit diagram of tri state gate ? Q. Draw Circuit diagram of tri state gate ?– Standard TTL, 74 series – Schottky TTL, 74S series – Low power Schottky TTL, 74LS series (LS-TTL) – Advanced Schottky TTL, 74AS series (AS-TTL) – Advanced low power Schottky TTL, 74ALS series – 74F fast TTL – 74LVC (low voltage CMOS) – 74ALVC (advanced low voltage CMOS) IC Nomenclature © Dept. of ECE,KRGCEW – 74LV (low voltage) – 74AVC (advanced very low voltage CMOS) – 74AUC (advanced ultra-low voltage CMOS) – 74AUP (advanced ultra-low power) – 74CBT (cross bar technology) – 74CBTLV (cross bar technology low voltage) – 74GTLP (gunning transceiver logic plus) – 74SSTV (stub series terminated logic) – 74TVC (translation voltage clamp)Comparison of logic families • Fan-out • Propagation delay • Power consumption • Speed © Dept. of ECE,KRGCEW • Noise margin • Voltage swing … etc… – ( Refer Page no. 247, Digital Electronics & Logic Design – B. Somanathan Nair)Monostable multivibrator • A monostable multivibrator has only one stable state and the other is quasi stable state. • When triggered, it changes from stable state to its quasi © Dept. of ECE,KRGCEW stable state and remains there for a specified duration before returning automatically to its stable state.Monostable ckts using NAND gates © Dept. of ECE,KRGCEWApplications • Gating • Time delays • Synchronizing • Detection of missing pulses © Dept. of ECE,KRGCEW Q. Astable Multivibrator circuit using Gates ? Q. Astable Multivibrator circuit using Gates ?Finite State Machines Finite State MachinesSequential Circuits • Also Called FSM(Finite State Machine) – Synchronous Sequential Circuits(SSLC) • Clock signal controls the operation – Asynchronous Sequential Circuits(ASLC) • No Clock Signal is required to control the operation © Dept. of ECE,KRGCEW • Different FSM Models – Mealy Models • Outputs depend on both the present state and primary inputs of the circuit – Moore Models • Outputs depend only on the present state of the circuitMealy Model Basic Sequential Circuit Models Combinational Logic Memory Primary Inputs Feedback Inputs Outputs Moore Model Combinational Logic Memory Primary Inputs Feedback Inputs OutputsSSLC Design Steps • State Diagram – Represents the sequence through which the machine should pass on. From this, the state table is prepared • State table – Shows the present and next states circuits and the inputs to get the required transitions © Dept. of ECE,KRGCEW • State Assignment – Assigning various states with their binary equivalent codes. • State Reduction – To obtain the simplified Logic equations to get the state transition. For eg: K-Map methodØ Selection of model Ø Mealy Model ü © Dept. of ECE,KRGCEW Ø Moore Model CLK CLKSynchronous Sequence Detector • Circuit that can be used to detect whether a given sequence of bits has been received or not by the receiver. Q. Draw the state diagram of a sequence detector which detects the Sequences 101 with a)Nonoverllappin and b)overlapping sequences. © Dept. of ECE,KRGCEW overlapping Answer: a) i/p 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 o/p 1 1 1 b) i/p 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 o/p 1 1 1 1 1Without Repetition © Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEWWith Repetition © Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEWState Table (Mealy model) (for Repetition case) Present State y Next State Y /Output z © Dept. of ECE,KRGCEW X=0 X=1 A A/0 B/0 B C/0 B/0 C A/0 B/1State Transition Table Present State Next State Y /Output z y1y2 X=0 Y1Y2 /z X=1 Y1Y2 /z © Dept. of ECE,KRGCEW A 0 0 A/0 0 0/0 B/0 0 1/0 B 0 1 C/0 1 1/0 B/0 0 1/0 C 1 1 A/0 0 0/0 B/1 0 1/1 State AssignmentState Reduction 0 1 0 X 0 0 0 X 00 01 11 10 01 y1y2 x 0 1 0 X 1 1 1 X 00 01 11 10 01 y1y2 x © Dept. of ECE,KRGCEW 0 0 0 X 0 0 1 X 00 01 11 10 01 y1y2 x _ _ Y1= x y1y2 _ Y2= x + y1y2 Z= x y1 D1= D2=Logic Diagram © Dept. of ECE,KRGCEW CLKState Table Present State y Next State Y /Output z Q. Design a sequence detector for the same state diagram(with repetition) with T flip flops ??? © Dept. of ECE,KRGCEW X=0 X=1 A A/0 B/0 B C/0 B/0 C A/0 B/1State Transition Table using T F/F Present State Next State Y /Output z State of T F/F y1 y2 X=0 X=1 Y Y /z Y Y /z T T T T © Dept. of ECE,KRGCEW Y1Y2 Y1Y2 T1 T2 T1 T2 A 0 0 0 0/0 0 1/0 0 0 0 1 B 0 1 1 1/0 0 1/0 1 0 0 0 C 1 1 0 0/0 0 1/1 1 1 1 0State Reduction 0 1 1 X 0 0 1 X 00 01 11 10 01 y1y2 x 0 0 1 X 1 0 0 X 00 01 11 10 01 y1y2 x © Dept. of ECE,KRGCEW 0 0 0 X 0 0 1 X 00 01 11 10 01 y1y2 x _ T1= x y2+y1 _ _ T2= xy1 + xy2 Z= x y1Logic Diagram © Dept. of ECE,KRGCEW CLKState Diagram – An Example • Draw the State Diagram of Sequence Detector to detect the sequence 1001 and 010 with repetition permitted in each case © Dept. of ECE,KRGCEW Answer: i/p 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 …… o/p 1 1 1 1 1© Dept. of ECE,KRGCEWOR © Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEW© Dept. of ECE,KRGCEWClass Assignment • Design of sequential serial adder (Page no. 173, Digital Electronics & Logic Design – B. Somanathan Nair) • Design of synchronous Mod 8 sequential counter © Dept. of ECE,KRGCEW (Page no. 179, Digital Electronics & Logic Design – B. Somanathan Nair) • Analysis of synchronous sequential serial adder (Page no. 181, Digital Electronics & Logic Design – B. Somanathan Nair)Synchronous Sequential Circuits (Moore model optional) q Design a Moore circuit that meets the following specification. 1. The circuit has one input w, and one output z 2. All changes in circuit occurs on +ve edge of clock signal © Dept. of ECE,KRGCEW 3. z = 1 if w was equal to 1 for two immediately preceding clock cycles. Otherwise, z = 0Design Steps with Moore model contd contd.. .. CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 w 0 1 0 1 1 0 1 1 1 0 1 z 0 0 0 0 0 1 0 0 1 1 0 Ø Sequence of input & output Ø State Diagram © Dept. of ECE,KRGCEWØ State Table Design Steps contd .. Present State Next state Output Z W=0 W=1 A A B 0 B A C 0 C A C 1 Ø State Transition Table © Dept. of ECE,KRGCEW Present State Next state Outpu t Z W=0 W=1 y2y1 Y2Y1 Y2Y1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 1 1 X X X X X Ø State Assignment q A à 00 q B à 01 q C à 10 Design Steps contd .. A General Sequential Circuit with input w, output z,and two state flip flip-flops(Moore type design) © Dept. of ECE,KRGCEWØ Choice of flip flip-flops and final output derivation Design Steps contd .. _ _ Y1 = wy1y2 © Dept. of ECE,KRGCEW Y2 = wy1+wy2 z = y2z D Q_Q Y2 y2 Design Steps contd .. Ø Final Implementation © Dept. of ECE,KRGCEW CLK w D QQ_Q Y1 y1Asynchronous Sequential Logic Circuits • Independent of CLK signal • Depend only on delay of various gates used in the circuit • Propagation delay is in the order of nanoseconds © Dept. of ECE,KRGCEW (100ns delay => 10Mhz frequency) – For CLK is less than 10MHz , ASLC is faster – For CLK greater than 10 MHz, SSLC is faster • ASLCs are Classified as – Fundamental mode circuits (Level mode circuits) – Pulse mode circuits • Gate delays are used in FMC where as F/F Delays will be used in PMCStructure of ASLC © Dept. of ECE,KRGCEW ASLCRaces & Cycles Races & Cycles are the problems that occur in ASLCs • Races In case of two secondary variables change simultaneously, both changes will not occur at the same time due to the difference in propagation delays leads to race problem – Non critical race © Dept. of ECE,KRGCEW • The desired state is reached after passing through undesired states – Critical race • Desired state will not be reached. Machine will stuck in undesired state • Cycle • Transition favoring cycles. Reach a stable state after passing through a cycle Races & Cycles Present State Next State Y1Y2 When inputs x1x2= state y y _ _ _ _ Let the state transition table of an ASLC be © Dept. of ECE,KRGCEW y1y2 x1x2 _x1x2 x1x2 x1x2 A 00 00 10 01 11 B 01 00 11 01 11 C 11 00 10 11 11 D 10 00 10 11 11 Critical race Non Non-Critical race Q.Design an asynchronous Toggle Flip Flip-flop T Qn Qn+1 0 0 0 0 1 1 1 0 1 Step1. Truth Table Step2. Waveforms © Dept. of ECE,KRGCEW 1 1 0Step3. State Diagram © Dept. of ECE,KRGCEWStep 4. Flaw Table Present State Next State Y /Output z X=0 X=1 A A/0 B/0 B C/1 B/0 C C/1 D/1 D A/0 D/1 Present State Next State Y /Output z Step5. State Assigned Table © Dept. of ECE,KRGCEW X=0 X=1 00 00/0 01/0 01 11/1 01/0 11 11/1 10/1 10 00/0 10/10 1 1 0 0 0 1 1 00 01 11 10 01 y1y2 x 0 1 1 0 1 1 0 0 00 01 11 10 01 y1y2 x Step 6. State Reduction© Dept. of ECE,KRGCEW _ Y1= x y2+xy1 _ _ Y2= xy1 + xy2 0 1 1 0 0 0 1 1 00 01 11 10 01 y1y2 x _ _ Z = x y2+xy1Step 7. Logic Diagram Q T Y Y2 xy _xy2 © Dept. of ECE,KRGCEW T Flip-Flop Y1 xy1 _y1 _ xy1Q. Design an Asynchronous Mod 4 sequential Counter ? I/P A B C D E F G H A Answer: 1. © Dept. of ECE,KRGCEW O/PState Diagram A B C D 0/00 1/00 0/10 1/10 C/Q1Q0 2. © Dept. of ECE,KRGCEW H G F E 1/11 0/11 1/01 0/01 1/00 0/10 1/10 1/11 0/11 1/01 0/01 0/00Present State Next State /Output Q C=0 C=1 A A/00 B/00 B C/01 B/01 C C/01 D/01 D E/10 D/10 State Table State Transition Table Present State y2y1y0 Next State Y2Y1Y0 /Output Q1Q0 i/p C=0 i/p C=1 000 000/00 001/00 001 010/01 001/01 010 010/01 011/01 3. 4. © Dept. of ECE,KRGCEW E E/10 F/10 F G/11 F/11 G G/11 H/11 H A/00 H/00 011 100/10 011/10 100 100/10 101/10 101 110/11 101/11 110 110/11 111/11 111 000/00 111/00Obtain Logic Expressions • Y2 =? • Y1 =? • Y0 =? • Q =? 5. © Dept. of ECE,KRGCEW Q1 • Q0 =?Realization of Logic Circuit 6.Analyze the following Logic circuit ? ( or obtain the state diagram ) D Y Delay of the entire circuit © Dept. of ECE,KRGCEW C y Ideal Gates Without time delayAnalysis D Y 0 1 0 When D = C = y =0 àY = 0 © Dept. of ECE,KRGCEW 0 C 0 y 1 1 0 1Analysis D Y 0 1 1 © Dept. of ECE,KRGCEW 1 C 0 y 1 0 1 1 When D = C = 0, y =1 àY = 1Analysis D Y 1 0 1 When D =1 C =1 y =0 àY = 1 © Dept. of ECE,KRGCEW 0 C 1 y 1 1 0 0Analysis D Y 1 0 1 When D =1 C =1 y =0 àY = 1 © Dept. of ECE,KRGCEW 1 After Delay C 1 y 1 0 1 0Analysis D Y 1 0 1 © Dept. of ECE,KRGCEW 1 C 1 y 1 0 1 0 When D =1 C =1 y =1 àY = 1Present State Next State Y /Output z y When CD = 00 01 10 11 0 0/0 0/0 0/0 1/-1 1/1 1/1 0/-1/1 State Transition Table C D y Y 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 © Dept. of ECE,KRGCEW Present State y Next State Y /Output z When CD = 00 01 10 11 A A/0 A/0 A/0 B/-B B/1 B/1 A/-B/1 Flow Table 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1State Diagram © Dept. of ECE,KRGCEWState Equivalence Present State Next state Output Z Q . Eliminate the redundant states in the given state diagram ? Æ Two States Sj andSi are said to be equivalent if and only if for every possible input sequence, the same output sequence will be produced regardless of whether Sj or Si is in the initial stage © Dept. of ECE,KRGCEW W=0 W=1 A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0ÄP1 = (ABCDEFG) S (Group With Output 0 & 1) ÄP2 = (ABD) (CEFG) S (Check 0 & 1 successor of each group , If each successor group is in same group, Leave that group. For Eg : 0-successor of ABD à BDB ð B,D are in same group 1-successor of ABD à CFG ð C,F,G are in same group) ÄP3 = (ABD) (CEG) (F) S (Continue grouping) Solution: © Dept. of ECE,KRGCEW 3 ÄP4 = (AD) (B) (CEG) (F) ÄP5 = (AD) (B) (CEG) (F) S ( P5 = P4 à Stop) àStates, which are in same group are equivalent states. Delete all states except one in same group Present State Next state Output Z W=0 W=1 A B C 1 B D F 1 C F E 0 F E D 0 Final State Diagram Obtained :An Example © Dept. of ECE,KRGCEWA & B are equivalent states © Dept. of ECE,KRGCEWHazards • The unexpected(undesired) output occurred for a short period due to the difference in propagation delays is called Hazard. It is the unwanted switching transient. – Logic Hazards © Dept. of ECE,KRGCEW • Static Hazard • Dynamic Hazard – Essential Hazards – Function HazardsStatic Hazard © Dept. of ECE,KRGCEWDynamic Hazard _ _ Y=ABC+EF+D M1 M2 I/Ps Change to 1 at t = 0 1nS © Dept. of ECE,KRGCEW Let the propagation delay of NOT Gate = 1nS AND Gate & NAND Gate = 2nS Initially A,D,F=1 & B,C,E=0 àY=0 Then B,C,E Changes to 1 àM3 M4 Y Propagation delay of OR gate is not ShownEssential Hazards • Occurs only in sequential Circuits • Occurs if there is more than one data path with different time delays (containing both sequential & Combinational Circuits ) © Dept. of ECE,KRGCEW InputFunction Hazards • Occurs when more than one input change at same time • Let A=1(5V) , B=0(0V) be the two © Dept. of ECE,KRGCEW inputs of an OR gate. – Inputs Change occurs. – Let two inputs reach 1.8V at same time – A zero pulse occurs in between two 1 outputs (< 2V will be treated as 0)Prevention of Hazards • Logic Hazard can be prevented by adding redundant term 0 1 1 1 0 1 0 0 00 01 11 10 01AB C Redundant Term © Dept. of ECE,KRGCEW • Essential Hazards can be avoided by adding extra gates and delays to introduce same delays in all the paths • The only way prevent functional hazard is to control the inputs vary at the same time. This is an external parameter and is called synchronizer problem Logic Implementation of Relay Circuit D A C Open Contact Closed Contact © Dept. of ECE,KRGCEW _B _C _A • Write all possible paths • Series paths represent product terms • Parallel paths represent sum terms _ _ _ _ _ _ Z = D A + D C C A + B C A + B C A _ _ _ _ = D A + B C A + B C AHardware Description Language Hardware Description LanguageIntroduction To VHDL • Very high speed integrated circuit Hardware Description Language. • The original standard of VHDL was adopted in 1987 and called IEEE1076 © Dept. of ECE,KRGCEW • Revised in 1993 and called IEEE1164Documentation in VHDL code • Data objects – Signals(represents logic signals or wires in ckt) – Constants – Variables (Rarely used for describing logic ckts) © Dept. of ECE,KRGCEW Signal types • Bit & Bit vector type • Std logic & std logic vector type • Signed & unsigned type • Integer type • Boolean type etc..Documentation in VHDL code • Operators * , /, MOD , + , -, & , = , <= , > , < , >= , NOT , AND ,NAND, OR, NOR, XOR, XNOR etc.. • Entity declaration Input & output signals are specified using ENTITY declaration. © Dept. of ECE,KRGCEW Possible modes of signals in entity are IN , OUT , INOUT , BUFFER. • Architecture Provides the circuit details for an entity. It has two parts • Declarative part • Architecture body • Package Hold the VHDL code that is of general use, like code that define types etc..Classification of VHDL Programming model – Concurrent assignment • Simple signal assignment • Selected signal assignment • Conditional signal assignment • Generate statements – Sequential assignment • Process statement © Dept. of ECE,KRGCEW • If statement • Case statement • Loop statement • The order of concurrent assignment statements in an architecture body appear does not affect the meaning of the code. • But in sequential assignment , the sequence has significant importance._ VHDL code for Y = ( A B) + C LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY example IS PORT(a,b,c : IN STD_LOGIC; y : OUT STD_LOGIC); Definition of signals Importing Library files © Dept. of ECE,KRGCEW END example; ARCHITECTURE logic OF example IS BEGIN y<= (NOT a AND b)XOR c; END logic; Behavior of circuitASSIGNMENTS • Write VHDL code for • AND GATE • OR GATE © Dept. of ECE,KRGCEW • NAND GATE • NOR GATE • XOR GATE • XNOR GATE • Write VHDL code for Full AdderApplications ApplicationsApplications of Basic Digital Modules © Dept. of ECE,KRGCEW A Simple Traffic Light control systemApplication contd.. © Dept. of ECE,KRGCEW Simple Traffic Light – A Second ApproachApplication contd.. © Dept. of ECE,KRGCEWMod 3 counter Mod 3 synchronous sequence generator Q0 Q1 S0 S1 Q0 Q1 S0 S1 CLK A CLK BUser SIPO Shift Register CLK C ( Time period of CLK B ) x 3 Channel like Free space D/A converter &Transmitter Receiver & A/D converter Signal A Signal B Application contd.. © Dept. of ECE,KRGCEW Synchronization is required to eliminate mismatch b/w transmitter & receiver. Here, if CLK A = CLK B, then the De-Mux is said to be synchronized with Mux. called Time division multiplexing MUX DE-MUX Sequence Detector (Eg: 1001 ) (For security purpose) section section Signal C Astable Multivibrator ( 1 Hz ) CLK Application contd.. © Dept. of ECE,KRGCEW Data Bus 7 segment L C D displayThank You Thank You © Dept. of ECE,KRGCEW Dept. of Electronics & Communication Engineering K R Gouri Amma College of Engineering for Women www. krgce .in